Index: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 824)
+++ branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 827)
@@ -35,5 +35,4 @@
 #include <inttypes.h>
 #include <systemc>
-
 #include "caba_base_module.h"
 #include "multi_write_buffer.h"
@@ -307,29 +306,29 @@
     soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table;
 
-    const size_t                        m_srcid;
-    const size_t                        m_cc_global_id;
-    const size_t                        m_nline_width;
-    const size_t                        m_itlb_ways;
-    const size_t                        m_itlb_sets;
-    const size_t                        m_dtlb_ways;
-    const size_t                        m_dtlb_sets;
-    const size_t                        m_icache_ways;
-    const size_t                        m_icache_sets;
-    const paddr_t                       m_icache_yzmask;
-    const size_t                        m_icache_words;
-    const size_t                        m_dcache_ways;
-    const size_t                        m_dcache_sets;
-    const paddr_t                       m_dcache_yzmask;
-    const size_t                        m_dcache_words;
-    const size_t                        m_x_width;
-    const size_t                        m_y_width;
-    const size_t                        m_proc_id;
-    const uint32_t                      m_max_frozen_cycles;
-    const size_t                        m_paddr_nbits;
-    uint32_t                            m_debug_start_cycle;
-    bool                                m_debug_ok;
-
-    uint32_t                            m_dcache_paddr_ext_reset;
-    uint32_t                            m_icache_paddr_ext_reset;
+    const size_t   m_srcid;
+    const size_t   m_cc_global_id;
+    const size_t   m_nline_width;
+    const size_t   m_itlb_ways;
+    const size_t   m_itlb_sets;
+    const size_t   m_dtlb_ways;
+    const size_t   m_dtlb_sets;
+    const size_t   m_icache_ways;
+    const size_t   m_icache_sets;
+    const paddr_t  m_icache_yzmask;
+    const size_t   m_icache_words;
+    const size_t   m_dcache_ways;
+    const size_t   m_dcache_sets;
+    const paddr_t  m_dcache_yzmask;
+    const size_t   m_dcache_words;
+    const size_t   m_x_width;
+    const size_t   m_y_width;
+    const size_t   m_proc_id;
+    const uint32_t m_max_frozen_cycles;
+    const size_t   m_paddr_nbits;
+    uint32_t       m_debug_start_cycle;
+    bool           m_debug_ok;
+
+    uint32_t       m_dcache_paddr_ext_reset;
+    uint32_t       m_icache_paddr_ext_reset;
 
     ////////////////////////////////////////
@@ -344,21 +343,21 @@
     // debug variables
     /////////////////////////////////////////////
-    bool                                m_debug_previous_i_hit;
-    bool                                m_debug_previous_d_hit;
-    bool                                m_debug_activated;
+    bool m_debug_previous_i_hit;
+    bool m_debug_previous_d_hit;
+    bool m_debug_activated;
 
     ///////////////////////////////
     // Software visible REGISTERS
     ///////////////////////////////
-    sc_signal<uint32_t>     r_mmu_ptpr;      // page table pointer register
-    sc_signal<uint32_t>     r_mmu_mode;      // mmu mode register
-    sc_signal<uint32_t>     r_mmu_word_lo;   // mmu misc data low
-    sc_signal<uint32_t>     r_mmu_word_hi;   // mmu misc data hight
-    sc_signal<uint32_t>     r_mmu_ibvar;     // mmu bad instruction address
-    sc_signal<uint32_t>     r_mmu_dbvar;     // mmu bad data address
-    sc_signal<uint32_t>     r_mmu_ietr;      // mmu instruction error type
-    sc_signal<uint32_t>     r_mmu_detr;      // mmu data error type
-    uint32_t                r_mmu_params;    // read-only
-    uint32_t                r_mmu_release;   // read_only
+    sc_signal<uint32_t> r_mmu_ptpr;    // page table pointer register
+    sc_signal<uint32_t> r_mmu_mode;    // mmu mode register
+    sc_signal<uint32_t> r_mmu_word_lo; // mmu misc data low
+    sc_signal<uint32_t> r_mmu_word_hi; // mmu misc data hight
+    sc_signal<uint32_t> r_mmu_ibvar;   // mmu bad instruction address
+    sc_signal<uint32_t> r_mmu_dbvar;   // mmu bad data address
+    sc_signal<uint32_t> r_mmu_ietr;    // mmu instruction error type
+    sc_signal<uint32_t> r_mmu_detr;    // mmu data error type
+    uint32_t            r_mmu_params;  // read-only
+    uint32_t            r_mmu_release; // read_only
 
 
@@ -366,249 +365,247 @@
     // ICACHE FSM REGISTERS
     //////////////////////////////
-    sc_signal<int>          r_icache_fsm;               // state register
-    sc_signal<int>          r_icache_fsm_save;          // return state for coherence op
-    sc_signal<paddr_t>      r_icache_vci_paddr;         // physical address
-    sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
+    sc_signal<int>      r_icache_fsm;        // state register
+    sc_signal<int>      r_icache_fsm_save;   // return state for coherence op
+    sc_signal<paddr_t>  r_icache_vci_paddr;  // physical address
+    sc_signal<uint32_t> r_icache_vaddr_save; // virtual address from processor
 
     // icache miss handling
-    sc_signal<size_t>       r_icache_miss_way;          // selected way for cache update
-    sc_signal<size_t>       r_icache_miss_set;          // selected set for cache update
-    sc_signal<size_t>       r_icache_miss_word;         // word index ( cache update)
-    sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a miss
-    sc_signal<bool>         r_icache_miss_clack;        // waiting for a cleanup acknowledge
+    sc_signal<size_t>   r_icache_miss_way;   // selected way for cache update
+    sc_signal<size_t>   r_icache_miss_set;   // selected set for cache update
+    sc_signal<size_t>   r_icache_miss_word;  // word index ( cache update)
+    sc_signal<bool>     r_icache_miss_inval; // coherence request matching a miss
+    sc_signal<bool>     r_icache_miss_clack; // waiting for a cleanup acknowledge
 
     // coherence request handling
-    sc_signal<size_t>       r_icache_cc_way;            // selected way for cc update/inval
-    sc_signal<size_t>       r_icache_cc_set;            // selected set for cc update/inval
-    sc_signal<size_t>       r_icache_cc_word;           // word counter for cc update
-    sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
+    sc_signal<size_t>   r_icache_cc_way;        // selected way for cc update/inval
+    sc_signal<size_t>   r_icache_cc_set;        // selected set for cc update/inval
+    sc_signal<size_t>   r_icache_cc_word;       // word counter for cc update
+    sc_signal<bool>     r_icache_cc_need_write; // activate the cache for writing
 
     // coherence clack handling
-    sc_signal<bool>         r_icache_clack_req;         // clack request
-    sc_signal<size_t>       r_icache_clack_way;         // clack way
-    sc_signal<size_t>       r_icache_clack_set;         // clack set
+    sc_signal<bool>     r_icache_clack_req; // clack request
+    sc_signal<size_t>   r_icache_clack_way; // clack way
+    sc_signal<size_t>   r_icache_clack_set; // clack set
 
     // icache flush handling
-    sc_signal<size_t>       r_icache_flush_count;       // slot counter used for cache flush
+    sc_signal<size_t>   r_icache_flush_count; // slot counter used for cache flush
 
     // communication between ICACHE FSM and VCI_CMD FSM
-    sc_signal<bool>         r_icache_miss_req;           // cached read miss
-    sc_signal<bool>         r_icache_unc_req;            // uncached read miss
+    sc_signal<bool>     r_icache_miss_req; // cached read miss
+    sc_signal<bool>     r_icache_unc_req;  // uncached read miss
 
     // communication between ICACHE FSM and DCACHE FSM
-    sc_signal<bool>         r_icache_tlb_miss_req;       // (set icache/reset dcache)
-    sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
+    sc_signal<bool>     r_icache_tlb_miss_req;  // (set icache/reset dcache)
+    sc_signal<bool>     r_icache_tlb_rsp_error; // tlb miss response error
 
     // Flip-Flop in ICACHE FSM for saving the cleanup victim request
-    sc_signal<bool>         r_icache_cleanup_victim_req;
-    sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
+    sc_signal<bool>     r_icache_cleanup_victim_req;
+    sc_signal<paddr_t>  r_icache_cleanup_victim_nline;
 
     // communication between ICACHE FSM and CC_SEND FSM
-    sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
-    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
-    sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
-    sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
-    sc_signal<size_t>       r_icache_cc_send_updt_tab_idx;  // ICACHE cc_send update table index
+    sc_signal<bool>     r_icache_cc_send_req;          // ICACHE cc_send request
+    sc_signal<int>      r_icache_cc_send_type;         // ICACHE cc_send request type
+    sc_signal<paddr_t>  r_icache_cc_send_nline;        // ICACHE cc_send nline
+    sc_signal<size_t>   r_icache_cc_send_way;          // ICACHE cc_send way
+    sc_signal<size_t>   r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index
 
     // Physical address extension for data access
-    sc_signal<uint32_t>     r_icache_paddr_ext;             // CP2 register (if vci_address > 32)
+    sc_signal<uint32_t> r_icache_paddr_ext; // CP2 register (if vci_address > 32)
 
     ///////////////////////////////
     // DCACHE FSM REGISTERS
     ///////////////////////////////
-    sc_signal<int>          r_dcache_fsm;               // state register
-    sc_signal<int>          r_dcache_fsm_cc_save;       // return state for coherence op
-    sc_signal<int>          r_dcache_fsm_scan_save;     // return state for tlb scan op
+    sc_signal<int>      r_dcache_fsm;             // state register
+    sc_signal<int>      r_dcache_fsm_cc_save;     // return state for coherence op
+    sc_signal<int>      r_dcache_fsm_scan_save;   // return state for tlb scan op
     // registers written in P0 stage (used in P1 stage)
-    sc_signal<bool>         r_dcache_wbuf_req;          // WBUF must be written in P1 stage
-    sc_signal<bool>         r_dcache_updt_req;          // DCACHE must be updated in P1 stage
-    sc_signal<uint32_t>     r_dcache_save_vaddr;        // virtual address (from proc)
-    sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
-    sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
-    sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
-    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
-    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
-    sc_signal<size_t>       r_dcache_save_cache_word;   // selected word (from dcache)
+    sc_signal<bool>     r_dcache_wbuf_req;        // WBUF must be written in P1 stage
+    sc_signal<bool>     r_dcache_updt_req;        // DCACHE must be updated in P1 stage
+    sc_signal<uint32_t> r_dcache_save_vaddr;      // virtual address (from proc)
+    sc_signal<uint32_t> r_dcache_save_wdata;      // write data (from proc)
+    sc_signal<uint32_t> r_dcache_save_be;         // byte enable (from proc)
+    sc_signal<paddr_t>  r_dcache_save_paddr;      // physical address
+    sc_signal<size_t>   r_dcache_save_cache_way;  // selected way (from dcache)
+    sc_signal<size_t>   r_dcache_save_cache_set;  // selected set (from dcache)
+    sc_signal<size_t>   r_dcache_save_cache_word; // selected word (from dcache)
     // registers used by the Dirty bit sub-fsm
-    sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address
-    sc_signal<size_t>       r_dcache_dirty_way;         // way to invalidate in dcache
-    sc_signal<size_t>       r_dcache_dirty_set;         // set to invalidate in dcache
+    sc_signal<paddr_t>  r_dcache_dirty_paddr; // PTE physical address
+    sc_signal<size_t>   r_dcache_dirty_way;   // way to invalidate in dcache
+    sc_signal<size_t>   r_dcache_dirty_set;   // set to invalidate in dcache
 
     // communication between DCACHE FSM and VCI_CMD FSM
-    sc_signal<paddr_t>      r_dcache_vci_paddr;         // physical address for VCI command
-    sc_signal<uint32_t>     r_dcache_vci_wdata;         // write unc data for VCI command
-    sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
-    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable request (read/write)
-    sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable byte enable
-    sc_signal<uint32_t>     r_dcache_vci_unc_write;     // uncacheable data write request
-    sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
-    sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for a CAS
-    sc_signal<uint32_t>     r_dcache_vci_cas_new;       // new data value for a CAS
-    sc_signal<bool>         r_dcache_vci_ll_req;        // atomic read request LL
-    sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
-    sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
+    sc_signal<paddr_t>  r_dcache_vci_paddr;     // physical address for VCI command
+    sc_signal<uint32_t> r_dcache_vci_wdata;     // write unc data for VCI command
+    sc_signal<bool>     r_dcache_vci_miss_req;  // read miss request
+    sc_signal<bool>     r_dcache_vci_unc_req;   // uncacheable request (read/write)
+    sc_signal<uint32_t> r_dcache_vci_unc_be;    // uncacheable byte enable
+    sc_signal<uint32_t> r_dcache_vci_unc_write; // uncacheable data write request
+    sc_signal<bool>     r_dcache_vci_cas_req;   // atomic write request CAS
+    sc_signal<uint32_t> r_dcache_vci_cas_old;   // previous data value for a CAS
+    sc_signal<uint32_t> r_dcache_vci_cas_new;   // new data value for a CAS
+    sc_signal<bool>     r_dcache_vci_ll_req;    // atomic read request LL
+    sc_signal<bool>     r_dcache_vci_sc_req;    // atomic write request SC
+    sc_signal<uint32_t> r_dcache_vci_sc_data;   // SC data (command)
 
     //RWT: local cas
-    sc_signal<bool>         r_cas_islocal;
-    sc_signal<size_t>       r_cas_local_way;
-    sc_signal<size_t>       r_cas_local_set;
-    sc_signal<size_t>       r_cas_local_word;
+    sc_signal<bool>     r_cas_islocal;
+    sc_signal<size_t>   r_cas_local_way;
+    sc_signal<size_t>   r_cas_local_set;
+    sc_signal<size_t>   r_cas_local_word;
 
     // register used for XTN inval
-    sc_signal<size_t>       r_dcache_xtn_way;           // selected way (from dcache)
-    sc_signal<size_t>       r_dcache_xtn_set;           // selected set (from dcache)
+    sc_signal<size_t>   r_dcache_xtn_way; // selected way (from dcache)
+    sc_signal<size_t>   r_dcache_xtn_set; // selected set (from dcache)
 
     // handling dcache miss
-    sc_signal<int>          r_dcache_miss_type;         // depending on the requester
-    sc_signal<size_t>       r_dcache_miss_word;         // word index for cache update
-    sc_signal<size_t>       r_dcache_miss_way;          // selected way for cache update
-    sc_signal<size_t>       r_dcache_miss_set;          // selected set for cache update
-    sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
-    sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
+    sc_signal<int>      r_dcache_miss_type;  // depending on the requester
+    sc_signal<size_t>   r_dcache_miss_word;  // word index for cache update
+    sc_signal<size_t>   r_dcache_miss_way;   // selected way for cache update
+    sc_signal<size_t>   r_dcache_miss_set;   // selected set for cache update
+    sc_signal<bool>     r_dcache_miss_inval; // coherence request matching a miss
+    sc_signal<bool>     r_dcache_miss_clack; // waiting for a cleanup acknowledge
 
     // handling coherence requests
-    sc_signal<size_t>       r_dcache_cc_way;            // selected way for cc update/inval
-    sc_signal<size_t>       r_dcache_cc_set;            // selected set for cc update/inval
-    sc_signal<int>          r_dcache_cc_state;          // state of selected cache slot
-    sc_signal<size_t>       r_dcache_cc_word;           // word counter for cc update
-    sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
-    sc_signal<paddr_t>      r_dcache_cc_inval_addr;     // address for a cleanup transaction
-    sc_signal<uint32_t>     r_dcache_cc_inval_data_cpt;
+    sc_signal<size_t>   r_dcache_cc_way;        // selected way for cc update/inval
+    sc_signal<size_t>   r_dcache_cc_set;        // selected set for cc update/inval
+    sc_signal<int>      r_dcache_cc_state;      // state of selected cache slot
+    sc_signal<size_t>   r_dcache_cc_word;       // word counter for cc update
+    sc_signal<bool>     r_dcache_cc_need_write; // activate the cache for writing
+    sc_signal<paddr_t>  r_dcache_cc_inval_addr; // address for a cleanup transaction
+    sc_signal<uint32_t> r_dcache_cc_inval_data_cpt;
 
     // coherence clack handling
-    sc_signal<bool>         r_dcache_clack_req;         // clack request
-    sc_signal<size_t>       r_dcache_clack_way;         // clack way
-    sc_signal<size_t>       r_dcache_clack_set;         // clack set
+    sc_signal<bool>     r_dcache_clack_req; // clack request
+    sc_signal<size_t>   r_dcache_clack_way; // clack way
+    sc_signal<size_t>   r_dcache_clack_set; // clack set
 
     // dcache flush handling
-    sc_signal<size_t>       r_dcache_flush_count;       // slot counter used for cache flush
+    sc_signal<size_t>   r_dcache_flush_count; // slot counter used for cache flush
 
     // ll response handling
-    sc_signal<size_t>       r_dcache_ll_rsp_count;      // flit counter used for ll rsp
+    sc_signal<size_t>   r_dcache_ll_rsp_count; // flit counter used for ll rsp
 
     // used by the TLB miss sub-fsm
-    sc_signal<uint32_t>     r_dcache_tlb_vaddr;         // virtual address for a tlb miss
-    sc_signal<bool>         r_dcache_tlb_ins;           // target tlb (itlb if true)
-    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of pte
-    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;     // pte1 or first word of pte2
-    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;       // second word of pte2
-    sc_signal<size_t>       r_dcache_tlb_cache_way;     // selected way in dcache
-    sc_signal<size_t>       r_dcache_tlb_cache_set;     // selected set in dcache
-    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
-    sc_signal<size_t>       r_dcache_tlb_way;           // selected way in tlb
-    sc_signal<size_t>       r_dcache_tlb_set;           // selected set in tlb
+    sc_signal<uint32_t> r_dcache_tlb_vaddr;      // virtual address for a tlb miss
+    sc_signal<bool>     r_dcache_tlb_ins;        // target tlb (itlb if true)
+    sc_signal<paddr_t>  r_dcache_tlb_paddr;      // physical address of pte
+    sc_signal<uint32_t> r_dcache_tlb_pte_flags;  // pte1 or first word of pte2
+    sc_signal<uint32_t> r_dcache_tlb_pte_ppn;    // second word of pte2
+    sc_signal<size_t>   r_dcache_tlb_cache_way;  // selected way in dcache
+    sc_signal<size_t>   r_dcache_tlb_cache_set;  // selected set in dcache
+    sc_signal<size_t>   r_dcache_tlb_cache_word; // selected word in dcache
+    sc_signal<size_t>   r_dcache_tlb_way;        // selected way in tlb
+    sc_signal<size_t>   r_dcache_tlb_set;        // selected set in tlb
 
     // ITLB and DTLB invalidation
-    sc_signal<paddr_t>      r_dcache_tlb_inval_line;    // line index
-    sc_signal<size_t>       r_dcache_tlb_inval_set;     // tlb set counter
+    sc_signal<paddr_t>  r_dcache_tlb_inval_line; // line index
+    sc_signal<size_t>   r_dcache_tlb_inval_set;  // tlb set counter
 
     // communication between DCACHE FSM and ICACHE FSM
-    sc_signal<bool>         r_dcache_xtn_req;           // xtn request (caused by processor)
-    sc_signal<int>          r_dcache_xtn_opcode;        // xtn request type
+    sc_signal<bool>     r_dcache_xtn_req;    // xtn request (caused by processor)
+    sc_signal<int>      r_dcache_xtn_opcode; // xtn request type
 
     // Filp-Flop in DCACHE FSM for saving the cleanup victim request
-    sc_signal<bool>         r_dcache_cleanup_victim_req;
-    sc_signal<bool>         r_dcache_cleanup_victim_line_ncc;
-    sc_signal<bool>         r_dcache_cleanup_victim_updt_data;
-    sc_signal<paddr_t>      r_dcache_cleanup_victim_nline;
+    sc_signal<bool>     r_dcache_cleanup_victim_req;
+    sc_signal<bool>     r_dcache_cleanup_victim_line_ncc;
+    sc_signal<bool>     r_dcache_cleanup_victim_updt_data;
+    sc_signal<paddr_t>  r_dcache_cleanup_victim_nline;
 
     // communication between DCACHE FSM and CC_SEND FSM
-    sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
-    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
-    sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
-    sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
-    sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
+    sc_signal<bool>     r_dcache_cc_send_req;          // DCACHE cc_send request
+    sc_signal<int>      r_dcache_cc_send_type;         // DCACHE cc_send request type
+    sc_signal<paddr_t>  r_dcache_cc_send_nline;        // DCACHE cc_send nline
+    sc_signal<size_t>   r_dcache_cc_send_way;          // DCACHE cc_send way
+    sc_signal<size_t>   r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index
 
     // special registers for RWT
-    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;     // Register for cleanup with data (wb updt)
-    sc_signal<bool>         r_dcache_cc_cleanup_line_ncc;      // Register for cleanup with data (wb updt)
-    sc_signal<bool>         r_dcache_miss_victim_no_coherence; // Register for victim in no coherence mode
-    sc_signal<bool>         r_dcache_line_no_coherence;        // Register for line current in no coherence mode
-    sc_signal<bool>         r_dcache_dirty_save;
-    sc_signal<uint32_t>     r_cc_send_cpt_word;
-    sc_signal<uint32_t>     r_dcache_miss_data_cpt;
-    sc_signal<paddr_t>      r_dcache_miss_data_addr;
-    sc_signal<uint32_t>     r_dcache_xtn_flush_data_cpt;
-    sc_signal<paddr_t>      r_dcache_xtn_flush_addr_data;
-    sc_signal<int>          r_dcache_xtn_state;
-    sc_signal<paddr_t>      r_dcache_xtn_data_addr;
-    sc_signal<uint32_t>     r_dcache_xtn_data_cpt;
-    sc_signal<bool>         r_dcache_read_state;
+    sc_signal<bool>     r_dcache_cc_cleanup_updt_data; // Register for cleanup with data (wb updt)
+    sc_signal<bool>     r_dcache_cc_cleanup_line_ncc;  // Register for cleanup with data (wb updt)
+    sc_signal<bool>     r_dcache_dirty_save;
+    sc_signal<uint32_t> r_cc_send_cpt_word;
+    sc_signal<uint32_t> r_dcache_miss_data_cpt;
+    sc_signal<paddr_t>  r_dcache_miss_data_addr;
+    sc_signal<uint32_t> r_dcache_xtn_flush_data_cpt;
+    sc_signal<paddr_t>  r_dcache_xtn_flush_addr_data;
+    sc_signal<int>      r_dcache_xtn_state;
+    sc_signal<paddr_t>  r_dcache_xtn_data_addr;
+    sc_signal<uint32_t> r_dcache_xtn_data_cpt;
+    sc_signal<bool>     r_dcache_read_state;
 
     // dcache directory extension
-    int                     *r_dcache_content_state; // content state of one cache line
+    int                 *r_dcache_content_state; // content state of one cache line
     // Stats
-    int                     *r_dcache_dirty_word;    // use for compute number of words dirty per cleanup_data
-    bool                    *r_dcache_zombi_ncc;     // use for compute number of blocked write on ncc zombi line
+    int                 *r_dcache_dirty_word;    // use for compute number of words dirty per cleanup_data
+    bool                *r_dcache_zombi_ncc;     // use for compute number of blocked write on ncc zombi line
     //////////////////////////////////////////////////////////////////////////////////////
 
     ///////////////////////////////////
     // Physical address extension for data access
-    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
+    sc_signal<uint32_t> r_dcache_paddr_ext; // CP2 register (if vci_address > 32)
 
     ///////////////////////////////////
     // VCI_CMD FSM REGISTERS
     ///////////////////////////////////
-    sc_signal<int>          r_vci_cmd_fsm;
-    sc_signal<size_t>       r_vci_cmd_min;                  // used for write bursts
-    sc_signal<size_t>       r_vci_cmd_max;                  // used for write bursts
-    sc_signal<size_t>       r_vci_cmd_cpt;                  // used for write bursts
-    sc_signal<bool>         r_vci_cmd_imiss_prio;           // round-robin between imiss & dmiss
+    sc_signal<int>      r_vci_cmd_fsm;
+    sc_signal<size_t>   r_vci_cmd_min;        // used for write bursts
+    sc_signal<size_t>   r_vci_cmd_max;        // used for write bursts
+    sc_signal<size_t>   r_vci_cmd_cpt;        // used for write bursts
+    sc_signal<bool>     r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss
 
     ///////////////////////////////////
     // VCI_RSP FSM REGISTERS
     ///////////////////////////////////
-    sc_signal<int>          r_vci_rsp_fsm;
-    sc_signal<size_t>       r_vci_rsp_cpt;
-    sc_signal<bool>         r_vci_rsp_ins_error;
-    sc_signal<bool>         r_vci_rsp_data_error;
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;          // response FIFO to ICACHE FSM
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;          // response FIFO to DCACHE FSM
+    sc_signal<int>        r_vci_rsp_fsm;
+    sc_signal<size_t>     r_vci_rsp_cpt;
+    sc_signal<bool>       r_vci_rsp_ins_error;
+    sc_signal<bool>       r_vci_rsp_data_error;
+    GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM
+    GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM
 
 
     //RWT
-    GenericFifo<bool>       r_vci_rsp_fifo_rpktid;
-    GenericFifo<uint32_t>   r_cc_send_data_fifo;
+    GenericFifo<bool>     r_vci_rsp_fifo_rpktid;
+    GenericFifo<uint32_t> r_cc_send_data_fifo;
 
     ///////////////////////////////////
     //  CC_SEND FSM REGISTER
     ///////////////////////////////////
-    sc_signal<int>          r_cc_send_fsm;                  // state register
-    sc_signal<bool>         r_cc_send_last_client;          // 0 dcache / 1 icache
+    sc_signal<int>        r_cc_send_fsm;         // state register
+    sc_signal<bool>       r_cc_send_last_client; // 0 dcache / 1 icache
 
     ///////////////////////////////////
     //  CC_RECEIVE FSM REGISTER
     ///////////////////////////////////
-    sc_signal<int>          r_cc_receive_fsm;               // state register
-    sc_signal<bool>         r_cc_receive_data_ins;          // request to : 0 dcache / 1 icache
+    sc_signal<int>        r_cc_receive_fsm;      // state register
+    sc_signal<bool>       r_cc_receive_data_ins; // request to : 0 dcache / 1 icache
 
     // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM
-    sc_signal<size_t>       r_cc_receive_word_idx;          // word index
-    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_be;
-    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_data;
-    GenericFifo<bool>       r_cc_receive_updt_fifo_eop;
+    sc_signal<size_t>     r_cc_receive_word_idx;       // word index
+    GenericFifo<uint32_t> r_cc_receive_updt_fifo_be;
+    GenericFifo<uint32_t> r_cc_receive_updt_fifo_data;
+    GenericFifo<bool>     r_cc_receive_updt_fifo_eop;
 
     // communication between CC_RECEIVE FSM and ICACHE FSM
-    sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
-    sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
-    sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
-    sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
-    sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
-    sc_signal<paddr_t>      r_cc_receive_icache_nline;      // cache line physical address
+    sc_signal<bool>       r_cc_receive_icache_req;          // cc_receive to icache request
+    sc_signal<int>        r_cc_receive_icache_type;         // cc_receive type of request
+    sc_signal<size_t>     r_cc_receive_icache_way;          // cc_receive to icache way
+    sc_signal<size_t>     r_cc_receive_icache_set;          // cc_receive to icache set
+    sc_signal<size_t>     r_cc_receive_icache_updt_tab_idx; // cc_receive update table index
+    sc_signal<paddr_t>    r_cc_receive_icache_nline;        // cache line physical address
 
     // communication between CC_RECEIVE FSM and DCACHE FSM
-    sc_signal<bool>         r_cc_receive_dcache_req;              // cc_receive to dcache request
-    sc_signal<int>          r_cc_receive_dcache_type;             // cc_receive type of request
-    sc_signal<size_t>       r_cc_receive_dcache_way;              // cc_receive to dcache way
-    sc_signal<size_t>       r_cc_receive_dcache_set;              // cc_receive to dcache set
-    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;     // cc_receive update table index
-    sc_signal<paddr_t>      r_cc_receive_dcache_nline;            // cache line physical address
-    sc_signal<bool>         r_cc_receive_dcache_inval_is_config;  // inval from memcache is config
+    sc_signal<bool>       r_cc_receive_dcache_req;             // cc_receive to dcache request
+    sc_signal<int>        r_cc_receive_dcache_type;            // cc_receive type of request
+    sc_signal<size_t>     r_cc_receive_dcache_way;             // cc_receive to dcache way
+    sc_signal<size_t>     r_cc_receive_dcache_set;             // cc_receive to dcache set
+    sc_signal<size_t>     r_cc_receive_dcache_updt_tab_idx;    // cc_receive update table index
+    sc_signal<paddr_t>    r_cc_receive_dcache_nline;           // cache line physical address
+    sc_signal<bool>       r_cc_receive_dcache_inval_is_config; // inval from memcache is config
 
     ///////////////////////////////////
     //  DSPIN CLACK INTERFACE REGISTER
     ///////////////////////////////////
-    sc_signal<bool>         r_dspin_clack_req;
-    sc_signal<uint64_t>     r_dspin_clack_flit;
+    sc_signal<bool>       r_dspin_clack_req;
+    sc_signal<uint64_t>   r_dspin_clack_flit;
 
     //////////////////////////////////////////////////////////////////
@@ -616,10 +613,10 @@
     //////////////////////////////////////////////////////////////////
 
-    iss_t                       r_iss;
-    MultiWriteBuffer<paddr_t>   r_wbuf;
-    GenericCache<paddr_t>       r_icache;
-    GenericCache<paddr_t>       r_dcache;
-    GenericTlb<paddr_t>         r_itlb;
-    GenericTlb<paddr_t>         r_dtlb;
+    iss_t                     r_iss;
+    MultiWriteBuffer<paddr_t> r_wbuf;
+    GenericCache<paddr_t>     r_icache;
+    GenericCache<paddr_t>     r_dcache;
+    GenericTlb<paddr_t>       r_itlb;
+    GenericTlb<paddr_t>       r_dtlb;
 
     //////////////////////////////////////////////////////////////////
@@ -627,132 +624,98 @@
     //////////////////////////////////////////////////////////////////
 
-    sc_signal<paddr_t>                     r_dcache_llsc_paddr;
-    sc_signal<uint32_t>                    r_dcache_llsc_key;
-    sc_signal<uint32_t>                    r_dcache_llsc_count;
-    sc_signal<bool>                        r_dcache_llsc_valid;
-
-
-    sc_signal<bool>                        r_cache_frozen;
+    sc_signal<paddr_t>  r_dcache_llsc_paddr;
+    sc_signal<uint32_t> r_dcache_llsc_key;
+    sc_signal<uint32_t> r_dcache_llsc_count;
+    sc_signal<bool>     r_dcache_llsc_valid;
 
     ////////////////////////////////
     // Activity counters
     ////////////////////////////////
-    uint32_t m_cpt_dcache_data_read;           // DCACHE DATA READ
-    uint32_t m_cpt_dcache_data_write;          // DCACHE DATA WRITE
-    uint32_t m_cpt_dcache_dir_read;            // DCACHE DIR READ
-    uint32_t m_cpt_dcache_dir_write;           // DCACHE DIR WRITE
-
-    uint32_t m_cpt_icache_data_read;           // ICACHE DATA READ
-    uint32_t m_cpt_icache_data_write;          // ICACHE DATA WRITE
-    uint32_t m_cpt_icache_dir_read;            // ICACHE DIR READ
-    uint32_t m_cpt_icache_dir_write;           // ICACHE DIR WRITE
-
-    uint32_t m_cpt_frz_cycles;                 // number of cycles where the cpu is frozen
-    uint32_t m_cpt_total_cycles;               // total number of cycles
+    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
+
+    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
+
+    uint32_t m_cpt_frz_cycles;              // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;            // total number of cycles
 
     // Cache activity counters
-    uint32_t m_cpt_data_read;                  // total number of read data
-    uint32_t m_cpt_data_write;                 // total number of write data
+    uint32_t m_cpt_data_read;               // total number of read data
+    uint32_t m_cpt_data_write;              // total number of write data
     uint32_t m_cpt_data_write_back;
+    uint32_t m_cpt_data_write_miss;         // number of total write miss
+    uint32_t m_cpt_data_write_on_zombi;     // number of frozen cycles related to blocked write on ZOMBI line
+    uint32_t m_cpt_data_write_on_zombi_ncc; // number of frozen cycles related to blocked write on NCC ZOMBI line
     uint32_t m_cpt_data_cleanup;
     uint32_t m_cpt_data_sc;
-    uint32_t m_cpt_data_miss;                  // number of read miss
-    uint32_t m_cpt_ins_miss;                   // number of instruction miss
-    uint32_t m_cpt_unc_read;                   // number of read uncached
-    uint32_t m_cpt_write_cached;               // number of cached write
-    uint32_t m_cpt_ins_read;                   // number of instruction read
-    uint32_t m_cpt_ins_spc_miss;               // number of speculative instruction miss
-
-    uint32_t m_cost_write_frz;                 // number of frozen cycles related to write buffer
-    uint32_t m_cost_data_miss_frz;             // number of frozen cycles related to data miss
-    uint32_t m_cost_unc_read_frz;              // number of frozen cycles related to uncached read
-    uint32_t m_cost_ins_miss_frz;              // number of frozen cycles related to ins miss
-
-    uint32_t m_cpt_imiss_transaction;          // number of VCI instruction miss transactions
-    uint32_t m_cpt_dmiss_transaction;          // number of VCI data miss transactions
-    uint32_t m_cpt_unc_transaction;            // number of VCI uncached read transactions
-    uint32_t m_cpt_dunc_transaction;           // number of VCI uncached read transactions
-    uint32_t m_cpt_ll_transaction;             // number of VCI uncached read transactions
-    uint32_t m_cpt_write_transaction;          // number of VCI write transactions
-    uint32_t m_cpt_icache_unc_transaction;
-
-    uint32_t m_cost_imiss_transaction;         // cumulated duration for VCI IMISS transactions
-    uint32_t m_cost_dmiss_transaction;         // cumulated duration for VCI DMISS transactions
-    uint32_t m_cost_unc_transaction;           // cumulated duration for VCI UNC transactions
-    uint32_t m_cost_write_transaction;         // cumulated duration for VCI WRITE transactions
-    uint32_t m_cost_icache_unc_transaction;    // cumulated duration for VCI IUNC transactions
-    uint32_t m_length_write_transaction;       // cumulated length for VCI WRITE transactions
+    uint32_t m_cpt_dcache_miss;             // number of read miss
+    uint32_t m_cpt_icache_miss;             // number of instruction miss
+    uint32_t m_cpt_ins_read;                // number of instruction read
+
+    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
+    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
+
+    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
 
     // TLB activity counters
-    uint32_t m_cpt_ins_tlb_read;               // number of instruction tlb read
-    uint32_t m_cpt_ins_tlb_miss;               // number of instruction tlb miss
-    uint32_t m_cpt_ins_tlb_update_acc;         // number of instruction tlb update
-    uint32_t m_cpt_ins_tlb_occup_cache;        // number of instruction tlb occupy data cache line
-    uint32_t m_cpt_ins_tlb_hit_dcache;         // number of instruction tlb hit in data cache
-
-    uint32_t m_cpt_data_tlb_read;              // number of data tlb read
-    uint32_t m_cpt_data_tlb_miss;              // number of data tlb miss
-    uint32_t m_cpt_data_tlb_update_acc;        // number of data tlb update
-    uint32_t m_cpt_data_tlb_update_dirty;      // number of data tlb update dirty
-    uint32_t m_cpt_data_tlb_hit_dcache;        // number of data tlb hit in data cache
-    uint32_t m_cpt_data_tlb_occup_cache;       // number of data tlb occupy data cache line
+    uint32_t m_cpt_itlb_read;               // number of instruction tlb read
+    uint32_t m_cpt_itlb_miss;               // number of instruction tlb miss
+    uint32_t m_cpt_itlb_write;              // number of instruction tlb update
+
+    uint32_t m_cpt_dtlb_read;               // number of data tlb read
+    uint32_t m_cpt_dtlb_miss;               // number of data tlb miss
+    uint32_t m_cpt_dtlb_write;              // number of data tlb update
+
+    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
+
+    // coherence activity counters
+    uint32_t m_cpt_cleanup_data_not_dirty;  // number of total cleanup data without extra data flits
+    uint32_t m_cpt_cleanup_data_dirty_word; // number of total words dirty in cleanup data
+
+
+
+    // counters NOT implemented
+    uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer
+    uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read
+    uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions
+    uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions
+    uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions
+    uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions
+    uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions
+    uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions
+    uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty
+    uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache
+    uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache
+    uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss
+    uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc
+    uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc
+    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
+    uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions
+    uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions
+    uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions
+    uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions
+    uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands
+    uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets
+    uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets
+    uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets
+    uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets
+    uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets
+    uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets
+    uint32_t m_cpt_dunc_transaction; // number of VCI uncached read transactions
+    uint32_t m_cpt_ll_transaction; // number of VCI uncached read transactions
+    uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands
+    uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands
+    uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands
+    uint32_t m_cpt_unc_read; // number of read uncached
+    uint32_t m_cpt_write_cached; // number of cached write
     uint32_t m_cpt_tlb_occup_dcache;
 
-    uint32_t m_cost_ins_tlb_miss_frz;          // number of frozen cycles related to instruction tlb miss
-    uint32_t m_cost_data_tlb_miss_frz;         // number of frozen cycles related to data tlb miss
-    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
-    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
-    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
-    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
-    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
-
-    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
-    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
-    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
-    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
-    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
-    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
-    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
-    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
-
-    uint32_t m_cost_itlbmiss_transaction;      // cumulated duration for VCI instruction TLB miss transactions
-    uint32_t m_cost_itlb_ll_transaction;       // cumulated duration for VCI instruction TLB ll acc transactions
-    uint32_t m_cost_itlb_sc_transaction;       // cumulated duration for VCI instruction TLB sc acc transactions
-    uint32_t m_cost_dtlbmiss_transaction;      // cumulated duration for VCI data TLB miss transactions
-    uint32_t m_cost_dtlb_ll_transaction;       // cumulated duration for VCI data TLB ll acc transactions
-    uint32_t m_cost_dtlb_sc_transaction;       // cumulated duration for VCI data TLB sc acc transactions
-    uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions
-    uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions
-
-    // coherence activity counters
-    uint32_t m_cpt_cc_update_icache;           // number of coherence update instruction commands
-    uint32_t m_cpt_cc_update_dcache;           // number of coherence update data commands
-    uint32_t m_cpt_cc_inval_icache;            // number of coherence inval instruction commands
-    uint32_t m_cpt_cc_inval_dcache;            // number of coherence inval data commands
-    uint32_t m_cpt_cc_broadcast;               // number of coherence broadcast commands
-
-    uint32_t m_cost_updt_data_frz;             // number of frozen cycles related to coherence update data packets
-    uint32_t m_cost_inval_ins_frz;             // number of frozen cycles related to coherence inval instruction packets
-    uint32_t m_cost_inval_data_frz;            // number of frozen cycles related to coherence inval data packets
-    uint32_t m_cost_broadcast_frz;             // number of frozen cycles related to coherence broadcast packets
-
-    uint32_t m_cpt_cc_cleanup_ins;             // number of coherence cleanup packets
-    uint32_t m_cpt_cc_cleanup_data;            // number of coherence cleanup packets
-    uint32_t m_cpt_cleanup_data_not_dirty;     // number of total cleanup data without extra data flits
-    uint32_t m_cpt_cleanup_data_dirty_word;    // number of total words dirty in cleanup data
-    uint32_t m_cpt_data_write_miss;            // number of total write miss
-    uint32_t m_cpt_data_write_on_zombi;        // number of frozen cycles related to blocked write on line NCC/CC ZOMBI
-    uint32_t m_cpt_data_write_on_zombi_ncc;    // number of frozen cycles related to blocked write on line NCC ZOMBI
-
-    uint32_t m_cpt_icleanup_transaction;       // number of instruction cleanup transactions
-    uint32_t m_cpt_dcleanup_transaction;       // number of instructinumber of data cleanup transactions
-    uint32_t m_cost_icleanup_transaction;      // cumulated duration for VCI instruction cleanup transactions
-    uint32_t m_cost_dcleanup_transaction;      // cumulated duration for VCI data cleanup transactions
-
-    uint32_t m_cost_ins_tlb_inval_frz;         // number of frozen cycles related to checking ins tlb invalidate
-    uint32_t m_cpt_ins_tlb_inval;              // number of ins tlb invalidate
-
-    uint32_t m_cost_data_tlb_inval_frz;        // number of frozen cycles related to checking data tlb invalidate
-    uint32_t m_cpt_data_tlb_inval;             // number of data tlb invalidate
 
     // FSM activity counters
@@ -764,6 +727,6 @@
     uint32_t m_cpt_fsm_cc_send    [64];
 
-    uint32_t m_cpt_stop_simulation;     // used to stop simulation if frozen
-    bool     m_monitor_ok;              // used to debug cache output
+    uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen
+    bool     m_monitor_ok;          // used to debug cache output
     uint32_t m_monitor_base;
     uint32_t m_monitor_length;
@@ -774,26 +737,26 @@
 public:
     VciCcVCacheWrapper(
-        sc_module_name                      name,
-        const int                           proc_id,
-        const soclib::common::MappingTable  &mtd,
-        const soclib::common::IntTab        &srcid,
-        const size_t                        cc_global_id,
-        const size_t                        itlb_ways,
-        const size_t                        itlb_sets,
-        const size_t                        dtlb_ways,
-        const size_t                        dtlb_sets,
-        const size_t                        icache_ways,
-        const size_t                        icache_sets,
-        const size_t                        icache_words,
-        const size_t                        dcache_ways,
-        const size_t                        dcache_sets,
-        const size_t                        dcache_words,
-        const size_t                        wbuf_nlines,
-        const size_t                        wbuf_nwords,
-        const size_t                        x_width,
-        const size_t                        y_width,
-        const uint32_t                      max_frozen_cycles,
-        const uint32_t                      debug_start_cycle,
-        const bool                          debug_ok );
+        sc_module_name                     name,
+        const int                          proc_id,
+        const soclib::common::MappingTable &mtd,
+        const soclib::common::IntTab       &srcid,
+        const size_t                       cc_global_id,
+        const size_t                       itlb_ways,
+        const size_t                       itlb_sets,
+        const size_t                       dtlb_ways,
+        const size_t                       dtlb_sets,
+        const size_t                       icache_ways,
+        const size_t                       icache_sets,
+        const size_t                       icache_words,
+        const size_t                       dcache_ways,
+        const size_t                       dcache_sets,
+        const size_t                       dcache_words,
+        const size_t                       wbuf_nlines,
+        const size_t                       wbuf_nwords,
+        const size_t                       x_width,
+        const size_t                       y_width,
+        const uint32_t                     max_frozen_cycles,
+        const uint32_t                     debug_start_cycle,
+        const bool                         debug_ok );
 
     ~VciCcVCacheWrapper();
