Ignore:
Timestamp:
Oct 15, 2014, 11:41:49 AM (10 years ago)
Author:
meunier
Message:

Trunk:

  • Cosmetic in mem_cache_directory.h and xram_transaction.h
  • Renamed mem_cache param dspin_in_width and dspin_out_width to memc_dspin_in_width and memc_dspin_out_width (because of a bug in soclib-cc ?). Should have updated these names in the .sd or .py files of all platforms
  • Updated the scripts for tsar_generic_xbar to take into account the ideal write-through + added a graph in create_graphs.py
File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r816 r836  
    13871387            int state;
    13881388            paddr_t tag;
    1389             size_t way = r_icache_flush_count.read()/m_icache_sets;
    1390             size_t set = r_icache_flush_count.read()%m_icache_sets;
     1389            size_t way = r_icache_flush_count.read() / m_icache_sets;
     1390            size_t set = r_icache_flush_count.read() % m_icache_sets;
    13911391
    13921392#ifdef INSTRUMENTATION
     
    24382438            if (m_dreq.type == iss_t::XTN_READ)
    24392439            {
    2440                 int xtn_opcode = (int)m_dreq.addr / 4;
     2440                int xtn_opcode = (int) m_dreq.addr / 4;
    24412441
    24422442                // checking processor mode:
     
    29722972
    29732973        // itlb miss request
    2974         else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss )
     2974        else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss)
    29752975        {
    29762976            r_dcache_tlb_ins    = true;
     
    31113111
    31123112            }
    3113             else if (entry & PTE_T_MASK ) //  PTD : me must access PT2
     3113            else if (entry & PTE_T_MASK) //  PTD : me must access PT2
    31143114            {
    31153115                // mark the cache line ac containing a PTD
     
    38473847            int     state;
    38483848            paddr_t tag;
    3849             size_t  way = r_dcache_flush_count.read()/m_dcache_sets;
    3850             size_t  set = r_dcache_flush_count.read()%m_dcache_sets;
     3849            size_t  way = r_dcache_flush_count.read() / m_dcache_sets;
     3850            size_t  set = r_dcache_flush_count.read() % m_dcache_sets;
    38513851
    38523852#ifdef INSTRUMENTATION
     
    44604460                r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
    44614461            }
    4462             if      (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
    4463             else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
    4464             else                                           r_dcache_fsm = DCACHE_IDLE;
     4462            if      (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
     4463            else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
     4464            else                                             r_dcache_fsm = DCACHE_IDLE;
    44654465        }
    44664466        break;
     
    47604760        }
    47614761
    4762         assert ( not r_dcache_cc_send_req.read() and
    4763         "CC_SEND must be available in DCACHE_CC_CHECK" );
     4762        assert(not r_dcache_cc_send_req.read() and
     4763        "CC_SEND must be available in DCACHE_CC_CHECK");
    47644764
    47654765        // Match between MISS address and CC address
     
    60216021        p_vci.trdid   = 0;
    60226022        p_vci.pktid   = TYPE_READ_INS_MISS;
    6023         p_vci.plen    = m_icache_words<<2;
     6023        p_vci.plen    = m_icache_words << 2;
    60246024        p_vci.cmd     = vci_param::CMD_READ;
    60256025        p_vci.eop     = true;
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