Changeset 845


Ignore:
Timestamp:
Oct 16, 2014, 10:57:42 AM (8 years ago)
Author:
cfuguet
Message:

reconf: introducing watchdog timer in the vci_cc_vcache_wrapper

  • The watchdog timer (r_dcache_miss_wdt) starts counting when there is a READ MISS in the cache.
  • It triggers an error to the processor when the waiting cycles are greater than a threshold defined in the reg r_dcache_miss_wdt_max.
Location:
branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

    r840 r845  
    266266        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
    267267        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read & Bus Error in cache access
     268        MMU_READ_DATA_TIMEOUT         = 0x1200, // Read & Watchdog timeout
    268269    };
    269270
     
    433434
    434435    // communication between DCACHE FSM and VCI_CMD FSM
    435     sc_signal<paddr_t>      r_dcache_vci_paddr;            // physical address for VCI command
    436     sc_signal<uint32_t>     r_dcache_vci_wdata;            // write unc data for VCI command
     436    sc_signal<paddr_t>      r_dcache_vci_paddr;         // physical address for VCI command
     437    sc_signal<uint32_t>     r_dcache_vci_wdata;         // write unc data for VCI command
    437438    sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
    438439    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable request (read/write)
     
    447448
    448449    // register used for XTN inval
    449     sc_signal<size_t>       r_dcache_xtn_way;            // selected way (from dcache)
    450     sc_signal<size_t>       r_dcache_xtn_set;            // selected set (from dcache)
     450    sc_signal<size_t>       r_dcache_xtn_way;           // selected way (from dcache)
     451    sc_signal<size_t>       r_dcache_xtn_set;           // selected set (from dcache)
    451452
    452453    // handling dcache miss
    453     sc_signal<int>            r_dcache_miss_type;            // depending on the requester
    454     sc_signal<size_t>       r_dcache_miss_word;            // word index for cache update
    455     sc_signal<size_t>       r_dcache_miss_way;            // selected way for cache update
    456     sc_signal<size_t>       r_dcache_miss_set;            // selected set for cache update
     454    sc_signal<int>          r_dcache_miss_type;         // depending on the requester
     455    sc_signal<size_t>       r_dcache_miss_word;         // word index for cache update
     456    sc_signal<size_t>       r_dcache_miss_way;          // selected way for cache update
     457    sc_signal<size_t>       r_dcache_miss_set;          // selected set for cache update
    457458    sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
    458459    sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
     460
     461    // Watchdog timer (WDT) for MISS timeout exception (black-hole detection)
     462    sc_signal<uint32_t>     r_dcache_miss_wdt_max;      // wdt triggering value
     463    sc_signal<uint32_t>     r_dcache_miss_wdt;          // wdt counter
    459464
    460465    // handling coherence requests
    461466    sc_signal<size_t>       r_dcache_cc_way;            // selected way for cc update/inval
    462467    sc_signal<size_t>       r_dcache_cc_set;            // selected set for cc update/inval
    463     sc_signal<size_t>       r_dcache_cc_word;            // word counter for cc update
     468    sc_signal<size_t>       r_dcache_cc_word;           // word counter for cc update
    464469    sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
    465470
    466471    // coherence clack handling
    467472    sc_signal<bool>         r_dcache_clack_req;         // clack request
    468     sc_signal<size_t>       r_dcache_clack_way;            // clack way
    469     sc_signal<size_t>       r_dcache_clack_set;            // clack set
     473    sc_signal<size_t>       r_dcache_clack_way;         // clack way
     474    sc_signal<size_t>       r_dcache_clack_set;         // clack set
    470475
    471476    // dcache flush handling
    472     sc_signal<size_t>       r_dcache_flush_count;        // slot counter used for cache flush
     477    sc_signal<size_t>       r_dcache_flush_count;       // slot counter used for cache flush
    473478
    474479    // ll response handling
    475     sc_signal<size_t>       r_dcache_ll_rsp_count;        // flit counter used for ll rsp
     480    sc_signal<size_t>       r_dcache_ll_rsp_count;      // flit counter used for ll rsp
    476481
    477482    // used by the TLB miss sub-fsm
    478     sc_signal<uint32_t>     r_dcache_tlb_vaddr;            // virtual address for a tlb miss
    479     sc_signal<bool>         r_dcache_tlb_ins;            // target tlb (itlb if true)
    480     sc_signal<paddr_t>      r_dcache_tlb_paddr;            // physical address of pte
    481     sc_signal<uint32_t>     r_dcache_tlb_pte_flags;        // pte1 or first word of pte2
    482     sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;        // second word of pte2
    483     sc_signal<size_t>       r_dcache_tlb_cache_way;        // selected way in dcache
    484     sc_signal<size_t>       r_dcache_tlb_cache_set;        // selected set in dcache
     483    sc_signal<uint32_t>     r_dcache_tlb_vaddr;         // virtual address for a tlb miss
     484    sc_signal<bool>         r_dcache_tlb_ins;           // target tlb (itlb if true)
     485    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of pte
     486    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;     // pte1 or first word of pte2
     487    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;       // second word of pte2
     488    sc_signal<size_t>       r_dcache_tlb_cache_way;     // selected way in dcache
     489    sc_signal<size_t>       r_dcache_tlb_cache_set;     // selected set in dcache
    485490    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
    486     sc_signal<size_t>       r_dcache_tlb_way;            // selected way in tlb
    487     sc_signal<size_t>       r_dcache_tlb_set;            // selected set in tlb
     491    sc_signal<size_t>       r_dcache_tlb_way;           // selected way in tlb
     492    sc_signal<size_t>       r_dcache_tlb_set;           // selected set in tlb
    488493
    489494    // ITLB and DTLB invalidation
     
    519524    sc_signal<size_t>       r_vci_cmd_min;                  // used for write bursts
    520525    sc_signal<size_t>       r_vci_cmd_max;                  // used for write bursts
    521     sc_signal<size_t>       r_vci_cmd_cpt;                    // used for write bursts
    522     sc_signal<bool>         r_vci_cmd_imiss_prio;            // round-robin between imiss & dmiss
     526    sc_signal<size_t>       r_vci_cmd_cpt;                  // used for write bursts
     527    sc_signal<bool>         r_vci_cmd_imiss_prio;           // round-robin between imiss & dmiss
    523528
    524529    ///////////////////////////////////
     
    529534    sc_signal<bool>         r_vci_rsp_ins_error;
    530535    sc_signal<bool>         r_vci_rsp_data_error;
    531     GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;            // response FIFO to ICACHE FSM
    532     GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;            // response FIFO to DCACHE FSM
     536    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;          // response FIFO to ICACHE FSM
     537    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;          // response FIFO to DCACHE FSM
    533538
    534539    ///////////////////////////////////
     
    551556
    552557    // communication between CC_RECEIVE FSM and ICACHE FSM
    553     sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
    554     sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
    555     sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
    556     sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
    557     sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
     558    sc_signal<bool>         r_cc_receive_icache_req;          // cc_receive to icache request
     559    sc_signal<int>          r_cc_receive_icache_type;         // cc_receive type of request
     560    sc_signal<size_t>       r_cc_receive_icache_way;          // cc_receive to icache way
     561    sc_signal<size_t>       r_cc_receive_icache_set;          // cc_receive to icache set
     562    sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx; // cc_receive update table index
    558563    sc_signal<paddr_t>      r_cc_receive_icache_nline;        // cache line physical address
    559564
    560565    // communication between CC_RECEIVE FSM and DCACHE FSM
    561     sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
    562     sc_signal<int>          r_cc_receive_dcache_type;       // cc_receive type of request
    563     sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
    564     sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
    565     sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;  // cc_receive update table index
     566    sc_signal<bool>         r_cc_receive_dcache_req;          // cc_receive to dcache request
     567    sc_signal<int>          r_cc_receive_dcache_type;         // cc_receive type of request
     568    sc_signal<size_t>       r_cc_receive_dcache_way;          // cc_receive to dcache way
     569    sc_signal<size_t>       r_cc_receive_dcache_set;          // cc_receive to dcache set
     570    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index
    566571    sc_signal<paddr_t>      r_cc_receive_dcache_nline;        // cache line physical address
    567572
  • branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r840 r845  
    331331      r_dcache_miss_set("r_dcache_miss_set"),
    332332      r_dcache_miss_inval("r_dcache_miss_inval"),
     333      r_dcache_miss_wdt_max("r_dcache_miss_wdt_max"),
     334      r_dcache_miss_wdt("r_dcache_miss_wdt"),
    333335
    334336      r_dcache_cc_way("r_dcache_cc_way"),
     
    811813
    812814        r_dcache_clack_req         = false;
     815
     816        // Reset watchdog timer threshold to max value
     817        r_dcache_miss_wdt_max      = UINT32_MAX;
    813818
    814819        // No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
     
    41424147            r_dcache_miss_set = set;
    41434148
     4149            // reset to 0 the miss watchdog timer
     4150            r_dcache_miss_wdt = 0;
     4151
    41444152            if (cleanup)
    41454153            {
     
    42654273            r_dcache_fsm = DCACHE_CC_CHECK;
    42664274            r_dcache_fsm_cc_save = r_dcache_fsm.read();
     4275            break;
     4276        }
     4277
     4278        // increment MISS watchdog timer for black-hole detection
     4279        r_dcache_miss_wdt = r_dcache_miss_wdt.read() + 1;
     4280        if (r_dcache_miss_wdt.read() == r_dcache_miss_wdt_max.read()) {
     4281            r_mmu_detr   = MMU_READ_DATA_TIMEOUT;
     4282            r_mmu_dbvar  = r_dcache_save_vaddr.read();
     4283            m_drsp.valid = true;
     4284            m_drsp.error = true;
     4285            r_dcache_fsm = DCACHE_IDLE;
    42674286            break;
    42684287        }
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