Index: trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 84)
+++ trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 88)
@@ -447,4 +447,5 @@
         r_itlb_k_read_dcache      = false;      
         r_itlb_acc_dcache_req     = false;   
+	r_itlb_acc_redo_req 	  = false;
         r_dcache_rsp_itlb_error   = false;
  
@@ -1368,4 +1369,9 @@
                     r_icache_fsm = ICACHE_ERROR;
                 } 
+	        else if ( r_itlb_acc_redo_req )
+		{
+		    r_itlb_acc_redo_req = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+		}
                 else  
                 {
@@ -1382,4 +1388,10 @@
                     r_icache_fsm = ICACHE_ERROR;
                 } 
+	        else if ( r_itlb_acc_redo_req )
+		{
+		    r_itlb_acc_redo_req = false;
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+		}
                 else  
                 {
@@ -1568,4 +1580,9 @@
                     r_icache_fsm = ICACHE_ERROR;
                 } 
+	        else if ( r_itlb_acc_redo_req )
+		{
+		    r_itlb_acc_redo_req = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+		}
                 else  
                 {
@@ -1582,4 +1599,10 @@
                     r_icache_fsm = ICACHE_ERROR;
                 } 
+	        else if ( r_itlb_acc_redo_req )
+		{
+		    r_itlb_acc_redo_req = false;
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+		}
                 else  
                 {
@@ -2258,5 +2281,6 @@
                 if ( !((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT) )
                 {
-                    r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+                    bool set_hit = r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+            	    assert(set_hit && "D$ IDLE ITLB set hit error");  
                 }
     	    }
@@ -2581,5 +2605,4 @@
 		dcache_hit_c = false;
             }
-
             if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
             {
@@ -2701,8 +2724,21 @@
                                         else    // get PTBA to calculate the physical address of PTE
                                         {
-                                            r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
-                                            r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
-                                            r_dcache_tlb_ptba_read = true;
-                                            r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+					    data_t ptba;
+            				    if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+					    {
+                                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                				r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                                            	r_dcache_tlb_ll_dirty_req = true;
+                                            	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+						
+					    }
+					    else
+					    {
+                                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                                r_dcache_tlb_ptba_read = true;
+                                                r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+					    }
                                         }
                                     }				
@@ -2813,7 +2849,17 @@
                                 {
                                     r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
-                                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
-                                    r_dcache_tlb_ptba_read = true;
-                                    r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+			            data_t ptba;
+            		            if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+			            {
+                			r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                                        r_dcache_tlb_ll_dirty_req = true;
+                                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+			            }
+				    else
+				    {
+                                        r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                        r_dcache_tlb_ptba_read = true;
+                                        r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+				    }
                                 }
                             }
@@ -2941,7 +2987,17 @@
 	                {
 	                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
-	                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
-	                    r_dcache_tlb_ptba_read = true;
-	                    r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+			    data_t ptba;
+            		    if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+			    {
+                	        r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                                r_dcache_tlb_ll_dirty_req = true;
+                                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+			    }
+			    else
+			    {
+                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                r_dcache_tlb_ptba_read = true;
+                                r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+			    }
 	                }
 	            }
@@ -3121,4 +3177,5 @@
             r_dcache_inval_tlb_rsp = false;
             r_dcache_fsm = DCACHE_IDLE;
+            if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
             break;
         }
@@ -3153,11 +3210,19 @@
                 if ( r_dcache_tlb_ptba_read )
                 {
+                    paddr_t tlb_dpaddr;
+		    data_t data;
                     r_dcache_tlb_ptba_read = false;
-                    //write_hit = r_dcache.write(((paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)), r_dcache_pte_update);
-                    //assert(write_hit && "Write on miss ignores data");
-                    r_dcache_tlb_ll_dirty_req = true;
-                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
-		    //m_cpt_dcache_data_write++; 
-                    m_cost_data_tlb_update_dirty_frz++;
+		    if (dcache_tlb.translate(dreq.addr, &tlb_dpaddr) && r_dcache.read( (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3) ,&data))
+		    {
+                        r_dcache_tlb_ll_dirty_req = true;
+                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+		        //m_cpt_dcache_data_write++; 
+                        m_cpt_data_tlb_update_dirty++;
+                        m_cost_data_tlb_update_dirty_frz++;
+ 		    }	        
+		    else
+		    {
+		    	r_dcache_fsm = DCACHE_IDLE;
+                    }
                 }
                 else
@@ -3181,8 +3246,5 @@
                         r_dcache_pte_update = tlb_data | PTE_L_MASK;
                         r_dcache_tlb_ll_acc_req = true;
-                	//write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK));  
-                	//assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
-			//m_cpt_dcache_data_write++; 
                         m_cpt_data_tlb_update_acc++;
                         m_cost_data_tlb_update_acc_frz++;
@@ -3200,8 +3262,5 @@
                         r_dcache_pte_update = tlb_data | PTE_R_MASK;
                         r_dcache_tlb_ll_acc_req = true;
-                	//write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK));  
-                	//assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
-			//m_cpt_dcache_data_write++; 
                         m_cpt_data_tlb_update_acc++;
                         m_cost_data_tlb_update_acc_frz++;
@@ -3381,4 +3440,5 @@
 		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
 		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
 		break;
             }
@@ -3388,4 +3448,5 @@
                 r_dcache_fsm = DCACHE_IDLE; 
             	r_dcache_inval_tlb_rsp = false;
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
 		break;
             }
@@ -3399,4 +3460,5 @@
                 r_dcache_fsm = DCACHE_IDLE;
                 r_dcache_inval_rsp = false;
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
                 break;
 	    }
@@ -3425,4 +3487,5 @@
             r_dcache_inval_tlb_rsp = false;
             r_dcache_fsm = DCACHE_IDLE;
+            if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
             break;
         }
@@ -3433,5 +3496,4 @@
             data_t   rsp_dtlb_miss = 0;
             paddr_t  victim_index = 0;
-	    //bool write_hit = false;
             size_t way = 0;
             size_t set = 0;
@@ -3445,4 +3507,5 @@
                 r_dcache_fsm = DCACHE_IDLE;
                 r_dcache_inval_rsp = false;
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
                 break;
             }
@@ -3487,4 +3550,5 @@
                 r_dcache_bad_vaddr  = dreq.addr;
                 r_dcache_fsm        = DCACHE_ERROR;
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
 	    }
 	    else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
@@ -3497,12 +3561,19 @@
                 if ( r_dcache_tlb_ptba_read )
                 {
+                    paddr_t tlb_dpaddr;
+		    data_t data;
                     r_dcache_tlb_ptba_read = false;
-                    //write_hit = r_dcache.write(((paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)),r_dcache_pte_update);
-                    //assert(write_hit && "Write on miss ignores data");
-                    r_dcache_tlb_ll_dirty_req = true;
-                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
-		    //m_cpt_dcache_data_write++; 
-                    m_cpt_data_tlb_update_dirty++;
-                    m_cost_data_tlb_update_dirty_frz++;
+		    if (dcache_tlb.translate(dreq.addr, &tlb_dpaddr) && r_dcache.read((paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3),&data))
+		    {
+                        r_dcache_tlb_ll_dirty_req = true;
+                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+		        //m_cpt_dcache_data_write++; 
+                        m_cpt_data_tlb_update_dirty++;
+                        m_cost_data_tlb_update_dirty_frz++;
+ 		    }	        
+		    else
+		    {
+		    	r_dcache_fsm = DCACHE_IDLE;
+                    }
                 }
                 else
@@ -3525,8 +3596,5 @@
                         r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK;
                         r_dcache_tlb_ll_acc_req = true;
-                	//write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK));  
-                	//assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
-			//m_cpt_dcache_data_write++; 
 			m_cpt_data_tlb_update_acc++;
                         m_cost_data_tlb_update_acc_frz++;
@@ -3544,8 +3612,5 @@
                         r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK;
                         r_dcache_tlb_ll_acc_req = true;
-                	//write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK));  
-                	//assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
-			//m_cpt_dcache_data_write++; 
 			m_cpt_data_tlb_update_acc++;
                         m_cost_data_tlb_update_acc_frz++;
@@ -3576,5 +3641,6 @@
                 r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false);
             }
-            r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+            bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+            assert(set_hit && "TLB1_UPDT set hit error");  
             r_dcache_fsm = DCACHE_IDLE;
         }
@@ -3610,5 +3676,4 @@
         data_t tlb_data = 0;
         data_t tlb_data_ppn = 0;
-	//bool write_hit = false;
         bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
 
@@ -3657,8 +3722,5 @@
 	        	r_dcache_ppn_update = tlb_data_ppn;
                         r_dcache_tlb_ll_acc_req = true;
-                	//write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK));  
-                	//assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
-			//m_cpt_dcache_data_write++; 
                         m_cpt_data_tlb_update_acc++;
                         m_cost_data_tlb_update_acc_frz++;
@@ -3678,8 +3740,5 @@
 	        	r_dcache_ppn_update = tlb_data_ppn;
                         r_dcache_tlb_ll_acc_req = true;
-                	//write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK));  
-                	//assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
-			//m_cpt_dcache_data_write++; 
                         m_cpt_data_tlb_update_acc++;
                         m_cost_data_tlb_update_acc_frz++;
@@ -3991,8 +4050,5 @@
 	        	r_dcache_ppn_update = tlb_data_ppn;
                         r_dcache_tlb_ll_acc_req = true;
-                	//write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK));  
-                	//assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
-			//m_cpt_dcache_data_write++; 
                         m_cpt_data_tlb_update_acc++;
                         m_cost_data_tlb_update_acc_frz++;
@@ -4012,8 +4068,5 @@
 	        	r_dcache_ppn_update = tlb_data_ppn;
                         r_dcache_tlb_ll_acc_req = true;
-                	//write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK));  
-                	//assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
-			//m_cpt_dcache_data_write++; 
                         m_cpt_data_tlb_update_acc++;
                         m_cost_data_tlb_update_acc_frz++;
@@ -4044,5 +4097,6 @@
                 r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false);
             }
-            r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+            bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+            assert(set_hit && "TLB2_UPDT set hit error");  
             r_dcache_fsm = DCACHE_IDLE;
         }
@@ -4143,4 +4197,5 @@
                 }
                 if (clean) break;
+		set = 0;
             }
 
@@ -4511,7 +4566,18 @@
                 {
                     r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
-                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
-                    r_dcache_tlb_ptba_read = true;
-                    r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+		    data_t ptba;
+            	    if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+		    {
+                        r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                    	r_dcache_tlb_ll_dirty_req = true;
+                    	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+		        
+		    }
+		    else
+		    {
+                        r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                        r_dcache_tlb_ptba_read = true;
+                        r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+		    }
                 }
             }
@@ -4680,5 +4746,6 @@
             r_dcache.update(r_icache_paddr_save, way, set, r_dcache_miss_buf);
 
-            r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+            bool set_hit = r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+            assert(set_hit && "ITLB_UPDT set hit error");  
             bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);	
             m_cpt_ins_tlb_occup_cache++; 
@@ -4771,4 +4838,6 @@
 	        if ( r_dcache_inval_rsp )
 	        {
+	            r_itlb_acc_dcache_req = false;
+	            r_itlb_acc_redo_req = true;
 	            r_dcache_inval_rsp = false;
 	            r_dcache_fsm = DCACHE_IDLE;
@@ -6009,2 +6078,3 @@
 
 
+
