Changeset 881


Ignore:
Timestamp:
Nov 12, 2014, 5:09:17 PM (8 years ago)
Author:
cfuguet
Message:

reconf: introduce a configuration function in the vci_xicu

  • This configuration function consists in a vector of writable registers (up to 32) which are directly connected to an output port (one port per register).
Location:
branches/reconfiguration/modules/vci_xicu
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • branches/reconfiguration/modules/vci_xicu/caba/metadata/vci_xicu.sd

    r880 r881  
    55__version__ = "$Revision$"
    66
    7 Module('caba:vci_xicu',
     7Module('caba:reconf:vci_xicu',
    88        classname = 'soclib::caba::VciXicu',
    99           tmpl_parameters = [
  • branches/reconfiguration/modules/vci_xicu/caba/source/include/vci_xicu.h

    r880 r881  
    22 *
    33 * SOCLIB_LGPL_HEADER_BEGIN
    4  * 
     4 *
    55 * This file is part of SoCLib, GNU LGPLv2.1.
    6  * 
     6 *
    77 * SoCLib is free software; you can redistribute it and/or modify it
    88 * under the terms of the GNU Lesser General Public License as published
    99 * by the Free Software Foundation; version 2.1 of the License.
    10  * 
     10 *
    1111 * SoCLib is distributed in the hope that it will be useful, but
    1212 * WITHOUT ANY WARRANTY; without even the implied warranty of
    1313 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
    1414 * Lesser General Public License for more details.
    15  * 
     15 *
    1616 * You should have received a copy of the GNU Lesser General Public
    1717 * License along with SoCLib; if not, write to the Free Software
    1818 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
    1919 * 02110-1301 USA
    20  * 
     20 *
    2121 * SOCLIB_LGPL_HEADER_END
    2222 *
     
    3939template<typename vci_param>
    4040class VciXicu
    41         : public caba::BaseModule
     41    : public caba::BaseModule
    4242{
    4343private:
     
    4949    const size_t                                    m_wti_count;
    5050    const size_t                                    m_irq_count;
     51    const size_t                                    m_cfg_count;
    5152
    5253    uint32_t*                                       r_msk_pti;
     
    5960    uint32_t                                        *r_pti_val;
    6061    uint32_t                                        *r_wti_reg;
     62    uint32_t                                        *r_cfg_reg;
    6163
    6264    uint32_t                                        m_clock_cycles;
    6365
    6466
    65     bool on_write( int                        seg, 
    66                    typename vci_param::addr_t addr, 
    67                    typename vci_param::data_t data, 
     67    bool on_write( int                        seg,
     68                   typename vci_param::addr_t addr,
     69                   typename vci_param::data_t data,
    6870                   int                        be );
    69     bool on_read(  int                        seg, 
    70                    typename vci_param::addr_t addr, 
     71    bool on_read(  int                        seg,
     72                   typename vci_param::addr_t addr,
    7173                   typename vci_param::data_t &data );
    7274
     
    8486    sc_core::sc_out<bool>*                         p_irq;
    8587    sc_core::sc_in<bool>*                          p_hwi;
     88    sc_core::sc_out<uint32_t>*                     p_cfg;
    8689
    8790    void print_trace( size_t channel );
    8891
    89         ~VciXicu();
     92    ~VciXicu();
    9093
    91         VciXicu(
    92                 sc_core::sc_module_name name,
    93                 const soclib::common::MappingTable &mt,
    94                 const soclib::common::IntTab &index,
    95         size_t pti_count,
    96         size_t hwi_count,
    97         size_t wti_count,
    98         size_t irq_count);
     94    VciXicu( sc_core::sc_module_name name,
     95             const soclib::common::MappingTable &mt,
     96             const soclib::common::IntTab &index,
     97             size_t pti_count,
     98             size_t hwi_count,
     99             size_t wti_count,
     100             size_t irq_count,
     101             size_t cfg_count = 0 );
    99102
    100103    soclib_static_assert(vci_param::B == 4);
  • branches/reconfiguration/modules/vci_xicu/caba/source/src/vci_xicu.cpp

    r880 r881  
    22 *
    33 * SOCLIB_LGPL_HEADER_BEGIN
    4  * 
     4 *
    55 * This file is part of SoCLib, GNU LGPLv2.1.
    6  * 
     6 *
    77 * SoCLib is free software; you can redistribute it and/or modify it
    88 * under the terms of the GNU Lesser General Public License as published
    99 * by the Free Software Foundation; version 2.1 of the License.
    10  * 
     10 *
    1111 * SoCLib is distributed in the hope that it will be useful, but
    1212 * WITHOUT ANY WARRANTY; without even the implied warranty of
    1313 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
    1414 * Lesser General Public License for more details.
    15  * 
     15 *
    1616 * You should have received a copy of the GNU Lesser General Public
    1717 * License along with SoCLib; if not, write to the Free Software
    1818 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
    1919 * 02110-1301 USA
    20  * 
     20 *
    2121 * SOCLIB_LGPL_HEADER_END
    2222 *
     
    5656
    5757//////////////////////////////////////////////////////
    58 tmpl(bool)::on_write( int                        seg, 
    59                       typename vci_param::addr_t addr, 
    60                       typename vci_param::data_t data, 
     58tmpl(bool)::on_write( int                        seg,
     59                      typename vci_param::addr_t addr,
     60                      typename vci_param::data_t data,
    6161                      int                        be)
    6262{
    63         size_t cell = (size_t)addr / vci_param::B;
    64         size_t idx = cell & 0x1f;
    65         size_t func = (cell >> 5) & 0x1f;
     63    size_t cell = (size_t)addr / vci_param::B;
     64    size_t idx = cell & 0x1f;
     65    size_t func = (cell >> 5) & 0x1f;
    6666
    6767    if ( be != 0xf )
    6868        return false;
    6969
    70         switch (func)
     70    switch (func)
    7171    {
    7272        case XICU_WTI_REG:
     
    7676
    7777#if SOCLIB_MODULE_DEBUG
    78 std::cout << "[" << name() << "] Write WTI_REG[" << std::dec << idx << "] = " 
     78std::cout << "[" << name() << "] Write WTI_REG[" << std::dec << idx << "] = "
    7979<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    8080#endif
     
    8484        CHECK_BOUNDS(pti);
    8585        r_pti_per[idx] = data;
    86         if ( !data ) 
     86        if ( !data )
    8787        {
    8888            r_pti_pending &= ~(1<<idx);
    8989            r_pti_val[idx] = 0;
    90         } 
    91         else if (r_pti_val[idx] == 0) 
     90        }
     91        else if (r_pti_val[idx] == 0)
    9292        {
    9393            r_pti_val[idx] = data;
     
    9595
    9696#if SOCLIB_MODULE_DEBUG
    97 std::cout << "[" << name() << "] Write PTI_PER[" << std::dec << idx << "] = " 
     97std::cout << "[" << name() << "] Write PTI_PER[" << std::dec << idx << "] = "
    9898<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    9999#endif
     
    105105
    106106#if SOCLIB_MODULE_DEBUG
    107 std::cout << "[" << name() << "] Write PTI_VAL[" << std::dec << idx << "] = " 
     107std::cout << "[" << name() << "] Write PTI_VAL[" << std::dec << idx << "] = "
    108108<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    109109#endif
     
    115115
    116116#if SOCLIB_MODULE_DEBUG
    117 std::cout << "[" << name() << "] Write MASK_PTI[" << std::dec << idx << "] = " 
     117std::cout << "[" << name() << "] Write MASK_PTI[" << std::dec << idx << "] = "
    118118<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    119119#endif
     
    125125
    126126#if SOCLIB_MODULE_DEBUG
    127 std::cout << "[" << name() << "] Write PTI_ENABLE[" << std::dec << idx << "] = " 
     127std::cout << "[" << name() << "] Write PTI_ENABLE[" << std::dec << idx << "] = "
    128128<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    129129#endif
     
    135135
    136136#if SOCLIB_MODULE_DEBUG
    137 std::cout << "[" << name() << "] Write PTI_DISABLE[" << std::dec << idx << "] = " 
     137std::cout << "[" << name() << "] Write PTI_DISABLE[" << std::dec << idx << "] = "
    138138<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    139139#endif
     
    145145
    146146#if SOCLIB_MODULE_DEBUG
    147 std::cout << "[" << name() << "] Write MSK_HWI[" << std::dec << idx << "] = " 
     147std::cout << "[" << name() << "] Write MSK_HWI[" << std::dec << idx << "] = "
    148148<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    149149#endif
     
    155155
    156156#if SOCLIB_MODULE_DEBUG
    157 std::cout << "[" << name() << "] Write HWI_ENABLE[" << std::dec << idx << "] = " 
     157std::cout << "[" << name() << "] Write HWI_ENABLE[" << std::dec << idx << "] = "
    158158<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    159159#endif
     
    165165
    166166#if SOCLIB_MODULE_DEBUG
    167 std::cout << "[" << name() << "] Write HWI_DISABLE[" << std::dec << idx << "] = " 
     167std::cout << "[" << name() << "] Write HWI_DISABLE[" << std::dec << idx << "] = "
    168168<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    169169#endif
     
    175175
    176176#if SOCLIB_MODULE_DEBUG
    177 std::cout << "[" << name() << "] Write MSK_WTI[" << std::dec << idx << "] = " 
     177std::cout << "[" << name() << "] Write MSK_WTI[" << std::dec << idx << "] = "
    178178<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    179179#endif
     
    185185
    186186#if SOCLIB_MODULE_DEBUG
    187 std::cout << "[" << name() << "] Write WTI_ENABLE[" << std::dec << idx << "] = " 
     187std::cout << "[" << name() << "] Write WTI_ENABLE[" << std::dec << idx << "] = "
    188188<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    189189#endif
     
    195195
    196196#if SOCLIB_MODULE_DEBUG
    197 std::cout << "[" << name() << "] Write WTI_DISABLE[" << std::dec << idx << "] = " 
    198 << std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    199 #endif
    200         return true;
    201         }
    202         return false;
     197std::cout << "[" << name() << "] Write WTI_DISABLE[" << std::dec << idx << "] = "
     198<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
     199#endif
     200        return true;
     201
     202        case XICU_CFG_REG:
     203        CHECK_BOUNDS(cfg);
     204        r_cfg_reg[idx] = data;
     205
     206#if SOCLIB_MODULE_DEBUG
     207std::cout << "[" << name() << "] Write CFG_REG[" << std::dec << idx << "] = "
     208<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
     209#endif
     210        return true;
     211    }
     212    return false;
    203213} // end on_write()
    204214
    205215/////////////////////////////////////////////////////
    206 tmpl(bool)::on_read( int                        seg, 
    207                      typename vci_param::addr_t addr, 
     216tmpl(bool)::on_read( int                        seg,
     217                     typename vci_param::addr_t addr,
    208218                     typename vci_param::data_t &data)
    209219{
    210         size_t cell = (size_t)addr / vci_param::B;
     220    size_t cell = (size_t)addr / vci_param::B;
    211221    size_t idx = cell & 0x1f;
    212         size_t func = (cell >> 5) & 0x1f;
    213 
    214         switch (func)
     222    size_t func = (cell >> 5) & 0x1f;
     223
     224    switch (func)
    215225    {
    216226    case XICU_WTI_REG:
    217227        CHECK_BOUNDS(wti);
    218228        data = r_wti_reg[idx];
    219         r_wti_pending &= ~(1<<idx);       
    220 
    221 #if SOCLIB_MODULE_DEBUG
    222 std::cout << "[" << name() << "] Read XICU_WTI_REG[" << std::dec << idx << "] = " 
     229        r_wti_pending &= ~(1<<idx);
     230
     231#if SOCLIB_MODULE_DEBUG
     232std::cout << "[" << name() << "] Read XICU_WTI_REG[" << std::dec << idx << "] = "
    223233<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    224234#endif
     
    230240
    231241#if SOCLIB_MODULE_DEBUG
    232 std::cout << "[" << name() << "] Read XICU_PTI_PER[" << std::dec << idx << "] = " 
     242std::cout << "[" << name() << "] Read XICU_PTI_PER[" << std::dec << idx << "] = "
    233243<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    234244#endif
     
    240250
    241251#if SOCLIB_MODULE_DEBUG
    242 std::cout << "[" << name() << "] Read XICU_PTI_VAL[" << std::dec << idx << "] = " 
     252std::cout << "[" << name() << "] Read XICU_PTI_VAL[" << std::dec << idx << "] = "
    243253<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    244254#endif
     
    251261
    252262#if SOCLIB_MODULE_DEBUG
    253 std::cout << "[" << name() << "] Read XICU_PTI_ACK[" << std::dec << idx << "] = " 
     263std::cout << "[" << name() << "] Read XICU_PTI_ACK[" << std::dec << idx << "] = "
    254264<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    255265#endif
     
    261271
    262272#if SOCLIB_MODULE_DEBUG
    263 std::cout << "[" << name() << "] Read XICU_MSK_PTI[" << std::dec << idx << "] = " 
     273std::cout << "[" << name() << "] Read XICU_MSK_PTI[" << std::dec << idx << "] = "
    264274<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    265275#endif
     
    271281
    272282#if SOCLIB_MODULE_DEBUG
    273 std::cout << "[" << name() << "] Read XICU_PTI_ACTIVE[" << std::dec << idx << "] = " 
     283std::cout << "[" << name() << "] Read XICU_PTI_ACTIVE[" << std::dec << idx << "] = "
    274284<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    275285#endif
     
    281291
    282292#if SOCLIB_MODULE_DEBUG
    283 std::cout << "[" << name() << "] Read XICU_MSK_HWI[" << std::dec << idx << "] = " 
     293std::cout << "[" << name() << "] Read XICU_MSK_HWI[" << std::dec << idx << "] = "
    284294<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    285295#endif
     
    291301
    292302#if SOCLIB_MODULE_DEBUG
    293 std::cout << "[" << name() << "] Read XICU_HWI_ACTIVE[" << std::dec << idx << "] = " 
     303std::cout << "[" << name() << "] Read XICU_HWI_ACTIVE[" << std::dec << idx << "] = "
    294304<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    295305#endif
     
    301311
    302312#if SOCLIB_MODULE_DEBUG
    303 std::cout << "[" << name() << "] Read XICU_MSK_WTI[" << std::dec << idx << "] = " 
     313std::cout << "[" << name() << "] Read XICU_MSK_WTI[" << std::dec << idx << "] = "
    304314<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    305315#endif
     
    311321
    312322#if SOCLIB_MODULE_DEBUG
    313 std::cout << "[" << name() << "] Read XICU_WTI_ACTIVE[" << std::dec << idx << "] = " 
     323std::cout << "[" << name() << "] Read XICU_WTI_ACTIVE[" << std::dec << idx << "] = "
    314324<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    315325#endif
     
    318328        case XICU_PRIO:
    319329        CHECK_BOUNDS(irq);
    320         data = 
     330        data =
    321331            (((r_msk_pti[idx] & r_pti_pending) ? 1 : 0) << 0) |
    322332            (((r_msk_hwi[idx] & r_hwi_pending) ? 1 : 0) << 1) |
     
    327337
    328338#if SOCLIB_MODULE_DEBUG
    329 std::cout << "[" << name() << "] Read XICU_PRIO[" << std::dec << idx << "] = " 
     339std::cout << "[" << name() << "] Read XICU_PRIO[" << std::dec << idx << "] = "
    330340<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
    331341#endif
     
    338348#endif
    339349        return true;
    340         }
    341         return false;
     350
     351    case XICU_CFG_REG:
     352        CHECK_BOUNDS(cfg);
     353        data = r_cfg_reg[idx];
     354
     355#if SOCLIB_MODULE_DEBUG
     356std::cout << "[" << name() << "] Read XICU_CFG_REG[" << std::dec << idx << "] = "
     357<< std::hex << (int)data << std::dec << " time = " << m_clock_cycles << std::endl;
     358#endif
     359        return true;
     360    }
     361    return false;
    342362} // end on_read()
    343363
     
    349369#endif
    350370
    351         if (!p_resetn.read())
    352     {
    353                 m_vci_fsm.reset();
    354 
    355         for ( size_t i = 0; i<m_pti_count; ++i ) 
     371    if (!p_resetn.read())
     372    {
     373        m_vci_fsm.reset();
     374
     375        for ( size_t i = 0; i<m_pti_count; ++i )
    356376        {
    357377            r_pti_per[i] = 0;
     
    362382            r_wti_reg[i] = 0;
    363383        }
    364         for ( size_t i = 0; i<m_irq_count; ++i ) 
     384        for ( size_t i = 0; i<m_irq_count; ++i )
    365385        {
    366386            r_msk_pti[i] = 0;
     
    368388            r_msk_hwi[i] = 0;
    369389        }
     390        for ( size_t i = 0; i<m_cfg_count; ++i )
     391        {
     392            r_cfg_reg[i] = 0;
     393        }
    370394        r_pti_pending = 0;
    371395        r_wti_pending = 0;
    372396        r_hwi_pending = 0;
    373397
    374                 return;
    375         }
     398        return;
     399    }
    376400
    377401    // update timer interrupt vector
    378     for ( size_t i = 0; i<m_pti_count; ++i ) 
     402    for ( size_t i = 0; i<m_pti_count; ++i )
    379403    {
    380404        uint32_t per = r_pti_per[i];
    381405
    382         if ( per && --r_pti_val[i] == 0 ) 
     406        if ( per && --r_pti_val[i] == 0 )
    383407        {
    384408            r_pti_pending |= 1<<i;
     
    387411    }
    388412
    389     // update pending hardware interrupt vector 
     413    // update pending hardware interrupt vector
    390414    uint32_t hwi_pending = 0;
    391415    for ( size_t i = 0; i<m_hwi_count; ++i )
     
    393417    r_hwi_pending = hwi_pending;
    394418
    395         m_vci_fsm.transition();
     419    m_vci_fsm.transition();
    396420}
    397421
     
    401425    assert( (channel < m_irq_count) and
    402426    "ERROR in XICU print_trace() : channel larger than proc number");
    403    
     427
    404428    std::cout << "XICU " << name() << std::hex
    405429              << " / HWI_MASK = " << r_msk_hwi[channel]
    406430              << " / SWI_MASK = " << r_msk_wti[channel]
    407               << " / PTI_MASK = " << r_msk_pti[channel] 
     431              << " / PTI_MASK = " << r_msk_pti[channel]
    408432              << " / HWI = " << r_hwi_pending
    409433              << " / WTI = " << r_wti_pending
     
    415439tmpl(void)::genMoore()
    416440{
    417         m_vci_fsm.genMoore();
     441    m_vci_fsm.genMoore();
    418442
    419443    // output irqs
    420     for ( size_t i = 0; i<m_irq_count; ++i ) 
     444    for ( size_t i = 0; i<m_irq_count; ++i )
    421445    {
    422446        bool b = (r_msk_pti[i] & r_pti_pending) ||
     
    428452#endif
    429453        p_irq[i] = b;
     454    }
     455
     456    // output cfg registers
     457    for ( size_t i = 0; i<m_cfg_count; ++i )
     458    {
     459        p_cfg[i] = r_cfg_reg[i];
    430460    }
    431461}
     
    438468                     size_t                  hwi_count,
    439469                     size_t                  wti_count,
    440                      size_t                  irq_count )
     470                     size_t                  irq_count,
     471                     size_t                  cfg_count )
    441472           : caba::BaseModule(name),
    442473           m_seglist(mt.getSegmentList(index)),
     
    446477           m_wti_count(wti_count),
    447478           m_irq_count(irq_count),
     479           m_cfg_count(cfg_count),
    448480           r_msk_pti(new uint32_t[irq_count]),
    449481           r_msk_wti(new uint32_t[irq_count]),
     
    469501        std::cout << "    => segment " << seg->name()
    470502                  << " / base = " << std::hex << seg->baseAddress()
    471                   << " / size = " << seg->size() << std::endl;
    472     }
    473  
    474         m_vci_fsm.on_read_write( on_read, on_write );
    475 
    476         SC_METHOD(transition);
    477         dont_initialize();
    478         sensitive << p_clk.pos();
    479 
    480         SC_METHOD(genMoore);
    481         dont_initialize();
    482         sensitive << p_clk.neg();
     503                  << " / size = " << seg->size() << std::endl;
     504    }
     505
     506    if ( cfg_count > 0 )
     507    {
     508        r_cfg_reg = new uint32_t[cfg_count];
     509        p_cfg = soclib::common::alloc_elems<sc_core::sc_out<uint32_t> >("cfg", cfg_count);
     510    }
     511
     512    m_vci_fsm.on_read_write( on_read, on_write );
     513
     514    SC_METHOD(transition);
     515    dont_initialize();
     516    sensitive << p_clk.pos();
     517
     518    SC_METHOD(genMoore);
     519    dont_initialize();
     520    sensitive << p_clk.neg();
    483521}
    484522
     
    494532    soclib::common::dealloc_elems(p_irq, m_irq_count);
    495533    soclib::common::dealloc_elems(p_hwi, m_hwi_count);
     534    if ( m_cfg_count > 0 )
     535    {
     536        delete [] r_cfg_reg;
     537        soclib::common::dealloc_elems(p_cfg, m_cfg_count);
     538    }
    496539}
    497540
  • branches/reconfiguration/modules/vci_xicu/include/soclib/xicu.h

    r880 r881  
    5353
    5454    XICU_CONFIG = 16,
     55
     56    XICU_CFG_REG = 17,
    5557};
    5658
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