Changeset 898


Ignore:
Timestamp:
Dec 2, 2014, 11:35:59 AM (9 years ago)
Author:
cfuguet
Message:

trunk: modify vci_block_device_tsar controller

  • The block device sends a VCI error response when a configuration command arrives and there is a pending transaction. This is to avoid a deadlock.

Until now, if a configuration command arrived, the TARGET FSM was
blocked until the previous transaction was finished and
acknowledged. If a processor tries to configure the block device
without acknowledging first a previous transaction, a dead-lock
situation was created.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp

    r895 r898  
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    2222 *
     
    4545tmpl(void)::transition()
    4646{
    47     if(p_resetn.read() == false) 
     47    if(p_resetn.read() == false)
    4848    {
    4949        r_initiator_fsm   = M_IDLE;
     
    5252        r_go              = false;
    5353        return;
    54     } 
     54    }
    5555
    5656    //////////////////////////////////////////////////////////////////////////////
     
    6363    case T_IDLE:
    6464    {
    65         if ( p_vci_target.cmdval.read() ) 
    66         { 
     65        if ( p_vci_target.cmdval.read() )
     66        {
    6767            r_srcid = p_vci_target.srcid.read();
    6868            r_trdid = p_vci_target.trdid.read();
     
    7272            bool found = false;
    7373            std::list<soclib::common::Segment>::iterator seg;
    74             for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) 
     74            for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ )
    7575            {
    7676                if ( seg->contains(address) ) found = true;
    7777            }
    78  
    79             bool                  read    = (p_vci_target.cmd.read() == vci_param::CMD_READ);
    80             uint32_t              cell    = (uint32_t)((address & 0x3F)>>2);
     78
     79            bool     read = (p_vci_target.cmd.read() == vci_param::CMD_READ);
     80            uint32_t cell = (uint32_t)((address & 0x3F)>>2);
     81            bool     pending = (r_initiator_fsm.read() != M_IDLE);
    8182
    8283            if     ( !read && not found )                         r_target_fsm = T_WRITE_ERROR;
     
    8485            else if( !read && not p_vci_target.eop.read() )       r_target_fsm = T_WRITE_ERROR;
    8586            else if(  read && not p_vci_target.eop.read() )       r_target_fsm = T_READ_ERROR;
     87            else if( !read && pending )                           r_target_fsm = T_WRITE_ERROR;
    8688            else if( !read && (cell == BLOCK_DEVICE_BUFFER) )     r_target_fsm = T_WRITE_BUFFER;
    8789            else if(  read && (cell == BLOCK_DEVICE_BUFFER) )     r_target_fsm = T_READ_BUFFER;
     
    100102
    101103            // get write data value for both 32 bits and 64 bits data width
    102             if( (vci_param::B == 8) and (p_vci_target.be.read() == 0xF0) ) 
     104            if( (vci_param::B == 8) and (p_vci_target.be.read() == 0xF0) )
    103105                r_tdata = (uint32_t)(p_vci_target.wdata.read()>>32);
    104106            else
     
    110112    case T_WRITE_BUFFER:
    111113    {
    112             if (p_vci_target.rspack.read() )
    113         {
    114             if (r_initiator_fsm.read() == M_IDLE)
    115             {
    116 
     114        if (p_vci_target.rspack.read() )
     115        {
    117116#if DEBUG_BDEV
    118117std::cout << "  <BDEV_TGT WRITE_BUFFER> value = " << r_tdata.read() << std::endl;
    119118#endif
    120                 r_buf_address = (uint64_t)r_tdata.read();
    121                 r_target_fsm  = T_IDLE;
    122                 }
     119            r_buf_address = (uint64_t)r_tdata.read();
     120            r_target_fsm  = T_IDLE;
    123121        }
    124122        break;
     
    127125    case T_WRITE_BUFFER_EXT:
    128126    {
    129         if (p_vci_target.rspack.read() )
    130         {
    131             if (r_initiator_fsm.read() == M_IDLE)
    132             {
    133 
     127        if (p_vci_target.rspack.read() )
     128        {
    134129#if DEBUG_BDEV
    135130std::cout << "  <BDEV_TGT WRITE_BUFFER_EXT> value = " << r_tdata.read() << std::endl;
    136131#endif
    137                 r_buf_address = r_buf_address.read() + (((uint64_t)r_tdata.read())<<32);
    138                 r_target_fsm  = T_IDLE;
    139             }
     132            r_buf_address = r_buf_address.read() + (((uint64_t)r_tdata.read())<<32);
     133            r_target_fsm  = T_IDLE;
    140134        }
    141135        break;
     
    144138    case T_WRITE_COUNT:
    145139    {
    146         if (p_vci_target.rspack.read() )
    147         {
    148             if (r_initiator_fsm.read() == M_IDLE)
    149             {
    150 
     140        if (p_vci_target.rspack.read() )
     141        {
    151142#if DEBUG_BDEV
    152143std::cout << "  <BDEV_TGT WRITE_COUNT> value = " << r_tdata.read() << std::endl;
    153144#endif
    154                 r_nblocks    = (uint32_t)r_tdata.read();
    155                 r_target_fsm = T_IDLE;
    156             }
     145            r_nblocks    = (uint32_t)r_tdata.read();
     146            r_target_fsm = T_IDLE;
    157147        }
    158148        break;
     
    161151    case T_WRITE_LBA:
    162152    {
    163         if (p_vci_target.rspack.read() )
    164         {
    165             if (r_initiator_fsm.read() == M_IDLE)
    166             {
    167 
     153        if (p_vci_target.rspack.read() )
     154        {
    168155#if DEBUG_BDEV
    169156std::cout << "  <BDEV_TGT WRITE_LBA> value = " << r_tdata.read() << std::endl;
    170157#endif
    171                 r_lba        = (uint32_t)r_tdata.read();
    172                 r_target_fsm = T_IDLE;
    173             }
     158            r_lba        = (uint32_t)r_tdata.read();
     159            r_target_fsm = T_IDLE;
    174160        }
    175161        break;
     
    178164    case T_WRITE_OP:
    179165    {
    180         if ( p_vci_target.rspack.read() ) 
     166        if ( p_vci_target.rspack.read() )
    181167        {
    182168            if ( ((uint32_t)r_tdata.read() == BLOCK_DEVICE_READ) and
     
    215201    case T_WRITE_IRQEN:
    216202    {
    217         if ( p_vci_target.rspack.read() ) 
     203        if ( p_vci_target.rspack.read() )
    218204        {
    219205
     
    243229    case T_READ_STATUS:
    244230    {
    245         if ( p_vci_target.rspack.read() ) 
     231        if ( p_vci_target.rspack.read() )
    246232        {
    247233            r_target_fsm = T_IDLE;
     
    254240    }
    255241    } // end switch target fsm
    256        
     242
    257243    //////////////////////////////////////////////////////////////////////////////
    258244    // The initiator FSM executes a loop, transfering one block per iteration.
     
    262248    //   and the number of bursts is (m_bursts_per_block).
    263249    // - If buffer not aligned, the number of bursts is (m_bursts_per_block + 1)
    264     //   and first and last burst are shorter, because all words in a burst 
     250    //   and first and last burst are shorter, because all words in a burst
    265251    //   must be contained in a single cache line.
    266252    //   first burst => nwords = m_words_per_burst - offset
     
    271257    switch( r_initiator_fsm.read() ) {
    272258    ////////////
    273     case M_IDLE:        // check buffer alignment to compute the number of bursts
    274     {
    275         if ( r_go.read() ) 
     259    case M_IDLE:    // check buffer alignment to compute the number of bursts
     260    {
     261        if ( r_go.read() )
    276262        {
    277263            r_index         = 0;
     
    285271
    286272            // start tranfer
    287             if ( r_read.read() )        r_initiator_fsm = M_READ_BLOCK;
     273            if ( r_read.read() )    r_initiator_fsm = M_READ_BLOCK;
    288274            else                    r_initiator_fsm = M_WRITE_BURST;
    289275        }
    290276        break;
    291     } 
     277    }
    292278    //////////////////
    293279    case M_READ_BLOCK:  // read one block from disk after waiting m_latency cycles
     
    297283            r_latency_count = m_latency;
    298284            ::lseek(m_fd, (r_lba + r_block_count)*m_words_per_block*4, SEEK_SET);
    299             if( ::read(m_fd, r_local_buffer, m_words_per_block*4) < 0 ) 
     285            if( ::read(m_fd, r_local_buffer, m_words_per_block*4) < 0 )
    300286            {
    301287                r_initiator_fsm = M_READ_ERROR;
    302288            }
    303             else   
     289            else
    304290            {
    305291                r_burst_count   = 0;
     
    309295
    310296////////////////////////////////////////////////////////////////////////////////////////
    311 //std::cout << "***** Block content after read for lba " 
     297//std::cout << "***** Block content after read for lba "
    312298//          << std::hex << r_lba.read() << " **************" << std::endl;
    313299//for ( size_t line=0 ; line<16 ; line++ )
     
    331317    //////////////////
    332318    case M_READ_BURST:  // Compute the number of words and the number of flits in the burst
    333                         // The number of flits can be smaller than the number of words 
     319                        // The number of flits can be smaller than the number of words
    334320                        // in case of 8 bytes flits...
    335321    {
     
    353339    }
    354340    ////////////////
    355     case M_READ_CMD:    // Send a multi-flits VCI WRITE command
     341    case M_READ_CMD:    // Send a multi-flits VCI WRITE command
    356342    {
    357343        if ( p_vci_initiator.cmdack.read() )
     
    359345            uint32_t nwords = r_burst_nwords.read() - r_words_count.read();
    360346
    361             if ( vci_param::B == 4 )    // one word per flit 
     347            if ( vci_param::B == 4 )    // one word per flit
    362348            {
    363349                if ( nwords <= 1 )      // last flit
     
    386372                    r_words_count = r_words_count.read() + 2;
    387373                }
    388                    
     374
    389375                // compute next word address and next local buffer index
    390376                if ( nwords == 1 )
     
    403389    }
    404390    ////////////////
    405     case M_READ_RSP:    // Wait a single flit VCI WRITE response
     391    case M_READ_RSP:    // Wait a single flit VCI WRITE response
    406392    {
    407393        if ( p_vci_initiator.rspval.read() )
     
    409395            bool aligned = (r_burst_offset.read() == 0);
    410396
    411             if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) 
     397            if ( (p_vci_initiator.rerror.read()&0x1) != 0 )
    412398            {
    413399                r_initiator_fsm = M_READ_ERROR;
    414400            }
    415             else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or 
     401            else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or
    416402                      (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) )
    417403            {
    418                 if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block 
     404                if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block
    419405                {
    420406                    r_initiator_fsm = M_READ_SUCCESS;
     
    465451    }
    466452    /////////////////
    467     case M_WRITE_CMD:   // This is actually a single flit VCI READ command
    468     {
    469             if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP;
     453    case M_WRITE_CMD:   // This is actually a single flit VCI READ command
     454    {
     455        if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP;
    470456        break;
    471457    }
    472458    /////////////////
    473     case M_WRITE_RSP:   // This is actually a multi-words VCI READ response
     459    case M_WRITE_RSP:   // This is actually a multi-words VCI READ response
    474460    {
    475461        if ( p_vci_initiator.rspval.read() )
     
    491477            if ( p_vci_initiator.reop.read() )  // last flit of the burst
    492478            {
    493                     r_words_count  = 0;
    494                 r_buf_address = r_buf_address.read() + (r_burst_nwords.read()<<2); 
    495 
    496                     if( (p_vci_initiator.rerror.read()&0x1) != 0 )
     479                r_words_count  = 0;
     480                r_buf_address = r_buf_address.read() + (r_burst_nwords.read()<<2);
     481
     482                if( (p_vci_initiator.rerror.read()&0x1) != 0 )
    497483                {
    498484                    r_initiator_fsm = M_WRITE_ERROR;
    499485                }
    500                 else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or 
     486                else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or
    501487                     (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst
    502488                {
     
    511497            else
    512498            {
    513                     r_words_count = r_words_count.read() + 1;
     499                r_words_count = r_words_count.read() + 1;
    514500            }
    515501        }
     
    517503    }
    518504    ///////////////////
    519     case M_WRITE_BLOCK:         // write a block to disk after waiting m_latency cycles
     505    case M_WRITE_BLOCK:     // write a block to disk after waiting m_latency cycles
    520506    {
    521507        if ( r_latency_count == 0 )
     
    523509
    524510////////////////////////////////////////////////////////////////////////////////////////
    525 //std::cout << "***** Block content before write for lba " 
     511//std::cout << "***** Block content before write for lba "
    526512//          << std::hex << r_lba.read() << " ***********" << std::endl;
    527513//for ( size_t line=0 ; line<16 ; line++ )
     
    540526            if( ::write(m_fd, r_local_buffer, m_words_per_block*4) < 0 )
    541527            {
    542                 r_initiator_fsm = M_WRITE_ERROR; 
    543             }
    544             else if ( r_block_count.read() == r_nblocks.read() - 1 ) 
    545             {
    546                 r_initiator_fsm = M_WRITE_SUCCESS; 
     528                r_initiator_fsm = M_WRITE_ERROR;
     529            }
     530            else if ( r_block_count.read() == r_nblocks.read() - 1 )
     531            {
     532                r_initiator_fsm = M_WRITE_SUCCESS;
    547533            }
    548534            else
     
    553539                r_initiator_fsm  = M_WRITE_BURST;
    554540            }
    555         } 
     541        }
    556542        else
    557543        {
     
    573559tmpl(void)::genMoore()
    574560{
    575     // p_vci_target port   
     561    // p_vci_target port
    576562    p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read();
    577563    p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read();
     
    591577        else if(r_initiator_fsm == M_READ_SUCCESS)  p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS;
    592578        else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS;
    593         else if(r_initiator_fsm == M_READ_ERROR)        p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR;
    594         else if(r_initiator_fsm == M_WRITE_ERROR)       p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR;
    595         else                                            p_vci_target.rdata = BLOCK_DEVICE_BUSY;
     579        else if(r_initiator_fsm == M_READ_ERROR)    p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR;
     580        else if(r_initiator_fsm == M_WRITE_ERROR)   p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR;
     581        else                                        p_vci_target.rdata = BLOCK_DEVICE_BUSY;
    596582        p_vci_target.rerror = VCI_READ_OK;
    597583        break;
     
    668654
    669655    switch (r_initiator_fsm) {
    670     case M_WRITE_CMD:           // It is actually a single flit VCI read command
     656    case M_WRITE_CMD:       // It is actually a single flit VCI read command
    671657        p_vci_initiator.rspack  = false;
    672658        p_vci_initiator.cmdval  = true;
    673659        p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read();
    674660        p_vci_initiator.cmd     = vci_param::CMD_READ;
    675         p_vci_initiator.pktid   = TYPE_READ_DATA_UNC; 
     661        p_vci_initiator.pktid   = TYPE_READ_DATA_UNC;
    676662        p_vci_initiator.wdata   = 0;
    677663        p_vci_initiator.be      = 0;
     
    679665        p_vci_initiator.eop     = true;
    680666        break;
    681     case M_READ_CMD:            // It is actually a multi-words VCI WRITE command
     667    case M_READ_CMD:        // It is actually a multi-words VCI WRITE command
    682668        p_vci_initiator.rspack  = false;
    683669        p_vci_initiator.cmdval  = true;
    684         p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); 
     670        p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read();
    685671        p_vci_initiator.cmd     = vci_param::CMD_WRITE;
    686672        p_vci_initiator.pktid   = TYPE_WRITE;
    687673        p_vci_initiator.plen    = (sc_dt::sc_uint<vci_param::K>)(r_burst_nwords.read()<<2);
    688         if ( (vci_param::B == 8) and ((r_burst_nwords.read() - r_words_count.read()) > 1) ) 
     674        if ( (vci_param::B == 8) and ((r_burst_nwords.read() - r_words_count.read()) > 1) )
    689675        {
    690676            p_vci_initiator.wdata = ((uint64_t)r_local_buffer[r_index.read()  ]) +
    691                                    (((uint64_t)r_local_buffer[r_index.read()+1]) << 32); 
     677                                   (((uint64_t)r_local_buffer[r_index.read()+1]) << 32);
    692678            p_vci_initiator.be    = 0xFF;
    693679            p_vci_initiator.eop   = ( (r_burst_nwords.read() - r_words_count.read()) <= 2 );
     
    713699    // IRQ signal
    714700    if ( ((r_initiator_fsm == M_READ_SUCCESS)  ||
    715               (r_initiator_fsm == M_WRITE_SUCCESS) ||
     701          (r_initiator_fsm == M_WRITE_SUCCESS) ||
    716702          (r_initiator_fsm == M_READ_ERROR)    ||
    717           (r_initiator_fsm == M_WRITE_ERROR) ) && 
    718          r_irq_enable.read() ) 
     703          (r_initiator_fsm == M_WRITE_ERROR) ) &&
     704         r_irq_enable.read() )
    719705    {
    720706
     
    723709            std::cout << "  <BDEV_INI send IRQ>" << std::endl;
    724710#endif
    725                 p_irq = true;
    726     } 
    727     else 
     711        p_irq = true;
     712    }
     713    else
    728714    {
    729715        p_irq = false;
     
    732718
    733719//////////////////////////////////////////////////////////////////////////////
    734 tmpl(/**/)::VciBlockDeviceTsar( sc_core::sc_module_name              name, 
     720tmpl(/**/)::VciBlockDeviceTsar( sc_core::sc_module_name              name,
    735721                                const soclib::common::MappingTable   &mt,
    736722                                const soclib::common::IntTab         &srcid,
     
    742728
    743729: caba::BaseModule(name),
    744         m_seglist(mt.getSegmentList(tgtid)),
    745         m_srcid(mt.indexForId(srcid)),
    746         m_words_per_block(block_size/4),
    747         m_words_per_burst(burst_size/4),
    748         m_bursts_per_block(block_size/burst_size),
    749         m_latency(latency),
    750         p_clk("p_clk"),
    751         p_resetn("p_resetn"),
    752         p_vci_initiator("p_vci_initiator"),
    753         p_vci_target("p_vci_target"),
    754         p_irq("p_irq")
     730    m_seglist(mt.getSegmentList(tgtid)),
     731    m_srcid(mt.indexForId(srcid)),
     732    m_words_per_block(block_size/4),
     733    m_words_per_burst(burst_size/4),
     734    m_bursts_per_block(block_size/burst_size),
     735    m_latency(latency),
     736    p_clk("p_clk"),
     737    p_resetn("p_resetn"),
     738    p_vci_initiator("p_vci_initiator"),
     739    p_vci_target("p_vci_target"),
     740    p_irq("p_irq")
    755741{
    756742    std::cout << "  - Building VciBlockDeviceTsar " << name << std::endl;
    757743
    758         SC_METHOD(transition);
     744    SC_METHOD(transition);
    759745    dont_initialize();
    760746    sensitive << p_clk.pos();
    761747
    762         SC_METHOD(genMoore);
     748    SC_METHOD(genMoore);
    763749    dont_initialize();
    764750    sensitive << p_clk.neg();
     
    766752    size_t nbsegs = 0;
    767753    std::list<soclib::common::Segment>::iterator seg;
    768     for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) 
     754    for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ )
    769755    {
    770756        nbsegs++;
    771        
    772             if ( (seg->baseAddress() & 0x0000003F) != 0 )
    773             {
    774                     std::cout << "Error in component VciBlockDeviceTsar : " << name
    775                               << "The base address of segment " << seg->name()
     757
     758        if ( (seg->baseAddress() & 0x0000003F) != 0 )
     759        {
     760            std::cout << "Error in component VciBlockDeviceTsar : " << name
     761                      << "The base address of segment " << seg->name()
    776762                      << " must be multiple of 64 bytes" << std::endl;
    777                     exit(1);
    778             }
    779             if ( seg->size() < 64 )
    780             {
    781                     std::cout << "Error in component VciBlockDeviceTsar : " << name
    782                           << "The size of segment " << seg->name()
     763            exit(1);
     764        }
     765        if ( seg->size() < 64 )
     766        {
     767            std::cout << "Error in component VciBlockDeviceTsar : " << name
     768                      << "The size of segment " << seg->name()
    783769                      << " cannot be smaller than 64 bytes" << std::endl;
    784                     exit(1);
    785             }
     770            exit(1);
     771        }
    786772        std::cout << "    => segment " << seg->name()
    787773                  << " / base = " << std::hex << seg->baseAddress()
    788                   << " / size = " << seg->size() << std::endl; 
     774                  << " / size = " << seg->size() << std::endl;
    789775    }
    790776
    791777    if( nbsegs == 0 )
    792778    {
    793                 std::cout << "Error in component VciBlockDeviceTsar : " << name
    794                           << " No segment allocated" << std::endl;
    795                 exit(1);
    796     }
    797 
    798     if( (block_size != 128)  && 
    799         (block_size != 256)  && 
    800         (block_size != 512)  && 
     779        std::cout << "Error in component VciBlockDeviceTsar : " << name
     780                  << " No segment allocated" << std::endl;
     781        exit(1);
     782    }
     783
     784    if( (block_size != 128)  &&
     785        (block_size != 256)  &&
     786        (block_size != 512)  &&
    801787        (block_size != 1024) &&
    802         (block_size != 2048) && 
     788        (block_size != 2048) &&
    803789        (block_size != 4096) )
    804         {
    805                 std::cout << "Error in component VciBlockDeviceTsar : " << name
    806                           << " The block size must be 128, 256, 512, 1024, 2048 or 4096 bytes"
     790    {
     791        std::cout << "Error in component VciBlockDeviceTsar : " << name
     792                  << " The block size must be 128, 256, 512, 1024, 2048 or 4096 bytes"
    807793                  << std::endl;
    808                 exit(1);
    809         }
    810 
    811     if( (burst_size != 8 ) && 
    812                 (burst_size != 16) &&
    813                 (burst_size != 32) &&
    814                 (burst_size != 64) )
    815         {
    816                 std::cout << "Error in component VciBlockDeviceTsar : " << name
    817                           << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl;
    818                 exit(1);
    819         }
    820 
    821         if ( (vci_param::B != 4) and (vci_param::B != 8) )
    822         {
    823                 std::cout << "Error in component VciBlockDeviceTsar : " << name             
    824                           << " The VCI data fields must have 32 bits or 64 bits" << std::endl;
    825                 exit(1);
    826         }
    827 
    828         m_fd = ::open(filename.c_str(), O_RDWR);
    829         if ( m_fd < 0 )
    830         {
    831                 std::cout << "Error in component VciBlockDeviceTsar : " << name
    832                           << " Unable to open file " << filename << std::endl;
    833                 exit(1);
    834         }
    835         m_device_size = lseek(m_fd, 0, SEEK_END) / block_size;
    836 
    837         if ( m_device_size > ((uint64_t)1<<vci_param::N ) )
    838         {
    839                 std::cout << "Error in component VciBlockDeviceTsar" << name
    840                           << " The file " << filename
    841                           << " has more blocks than addressable with the VCI address" << std::endl;
    842                 exit(1);
    843         }
    844 
    845         r_local_buffer = new uint32_t[m_words_per_block];
     794        exit(1);
     795    }
     796
     797    if( (burst_size != 8 ) &&
     798        (burst_size != 16) &&
     799        (burst_size != 32) &&
     800        (burst_size != 64) )
     801    {
     802        std::cout << "Error in component VciBlockDeviceTsar : " << name
     803                  << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl;
     804        exit(1);
     805    }
     806
     807    if ( (vci_param::B != 4) and (vci_param::B != 8) )
     808    {
     809        std::cout << "Error in component VciBlockDeviceTsar : " << name
     810                  << " The VCI data fields must have 32 bits or 64 bits" << std::endl;
     811        exit(1);
     812    }
     813
     814    m_fd = ::open(filename.c_str(), O_RDWR);
     815    if ( m_fd < 0 )
     816    {
     817        std::cout << "Error in component VciBlockDeviceTsar : " << name
     818                  << " Unable to open file " << filename << std::endl;
     819        exit(1);
     820    }
     821    m_device_size = lseek(m_fd, 0, SEEK_END) / block_size;
     822
     823    if ( m_device_size > ((uint64_t)1<<vci_param::N ) )
     824    {
     825        std::cout << "Error in component VciBlockDeviceTsar" << name
     826                  << " The file " << filename
     827                  << " has more blocks than addressable with the VCI address" << std::endl;
     828        exit(1);
     829    }
     830
     831    r_local_buffer = new uint32_t[m_words_per_block];
    846832
    847833} // end constructor
     
    858844tmpl(void)::print_trace()
    859845{
    860         const char* initiator_str[] =
    861     {
    862                 "INI_IDLE",
    863 
    864                 "INI_READ_BLOCK",
    865                 "INI_READ_BURST",
    866                 "INI_READ_CMD",
    867                 "INI_READ_RSP",
    868                 "INI_READ_SUCCESS",
    869                 "INI_READ_ERROR",
    870 
    871                 "INI_WRITE_BURST",
    872                 "INI_WRITE_CMD",
    873                 "INI_WRITE_RSP",
    874                 "INI_WRITE_BLOCK",
    875                 "INI_WRITE_SUCCESS",
    876                 "INI_WRITE_ERROR",
    877         };
    878         const char* target_str[] =
    879     {
    880                 "TGT_IDLE",
    881                 "TGT_WRITE_BUFFER",
    882                 "TGT_READ_BUFFER",
    883                 "TGT_WRITE_BUFFER_EXT",
    884                 "TGT_READ_BUFFER_EXT",
    885                 "TGT_WRITE_COUNT",
    886                 "TGT_READ_COUNT",
    887                 "TGT_WRITE_LBA",
    888                 "TGT_READ_LBA",
    889                 "TGT_WRITE_OP",
    890                 "TGT_READ_STATUS",
    891                 "TGT_WRITE_IRQEN",
    892                 "TGT_READ_IRQEN",
    893                 "TGT_READ_SIZE",
    894                 "TGT_READ_BLOCK",
    895                 "TGT_READ_ERROR",
    896                 "TGT_WRITE_ERROR ",
    897         };
    898 
    899         std::cout << "BDEV " << name()
    900               << " : " << target_str[r_target_fsm.read()] 
    901                       << " / " << initiator_str[r_initiator_fsm.read()]
     846    const char* initiator_str[] =
     847    {
     848        "INI_IDLE",
     849
     850        "INI_READ_BLOCK",
     851        "INI_READ_BURST",
     852        "INI_READ_CMD",
     853        "INI_READ_RSP",
     854        "INI_READ_SUCCESS",
     855        "INI_READ_ERROR",
     856
     857        "INI_WRITE_BURST",
     858        "INI_WRITE_CMD",
     859        "INI_WRITE_RSP",
     860        "INI_WRITE_BLOCK",
     861        "INI_WRITE_SUCCESS",
     862        "INI_WRITE_ERROR",
     863    };
     864    const char* target_str[] =
     865    {
     866        "TGT_IDLE",
     867        "TGT_WRITE_BUFFER",
     868        "TGT_READ_BUFFER",
     869        "TGT_WRITE_BUFFER_EXT",
     870        "TGT_READ_BUFFER_EXT",
     871        "TGT_WRITE_COUNT",
     872        "TGT_READ_COUNT",
     873        "TGT_WRITE_LBA",
     874        "TGT_READ_LBA",
     875        "TGT_WRITE_OP",
     876        "TGT_READ_STATUS",
     877        "TGT_WRITE_IRQEN",
     878        "TGT_READ_IRQEN",
     879        "TGT_READ_SIZE",
     880        "TGT_READ_BLOCK",
     881        "TGT_READ_ERROR",
     882        "TGT_WRITE_ERROR ",
     883    };
     884
     885    std::cout << "BDEV " << name()
     886              << " : " << target_str[r_target_fsm.read()]
     887              << " / " << initiator_str[r_initiator_fsm.read()]
    902888              << " / buf = " << std::hex << r_buf_address.read()
    903889              << " / lba = " << std::hex << r_lba.read()
    904                       << " / block_count = " << std::dec << r_block_count.read()
    905                       << " / burst_count = " << r_burst_count.read()
    906                       << " / word_count = " << r_words_count.read() <<std::endl;
     890              << " / block_count = " << std::dec << r_block_count.read()
     891              << " / burst_count = " << r_burst_count.read()
     892              << " / word_count = " << r_words_count.read() <<std::endl;
    907893}
    908894
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