Changeset 970

Timestamp:

Apr 6, 2015, 11:53:18 AM (9 years ago)

Author:

cfuguet

Message:

bugfix in vci_cc_vcache_wrapper: remove a wrong assert condition

• Remove a wrong assert condition on the treatment of external requests (CP2) for dcache and icache physical address invalidation.

Files:

• branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (2 diffs)
• trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (2 diffs)

branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -1139 +1139 @@
             else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV)
             {
-                if (sizeof(paddr_t) <= 32)
-                {
-                    assert(r_mmu_word_hi.read() == 0 &&
-                    "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
-                    r_icache_vci_paddr = (paddr_t) r_mmu_word_lo.read();
-                }
-                else
-                {
-                    r_icache_vci_paddr = (paddr_t) r_mmu_word_hi.read() << 32 |
-                                         (paddr_t) r_mmu_word_lo.read();
-                }
+                uint64_t pa = ((uint64_t)r_mmu_word_hi.read() << 32) |
+                              ((uint64_t)r_mmu_word_lo.read());
+
+                r_icache_vci_paddr = (paddr_t)pa;
                 r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
             }
@@ -2640 +2633 @@
 
                     case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
+                    {
+                        uint64_t pa = ((uint64_t)r_mmu_word_hi.read() << 32) |
+                                      ((uint64_t)r_mmu_word_lo.read());
+
+                        r_dcache_save_paddr = (paddr_t)pa;
                         r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
-                        if (sizeof(paddr_t) <= 32)
-                        {
-                            assert(r_mmu_word_hi.read() == 0 &&
-                            "high bits should be 0 for 32bit paddr");
-                            r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
-                        }
-                        else
-                        {
-                            r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 |
-                                                  (paddr_t)r_mmu_word_lo.read();
-                        }
                         break;
-
+                    }
                     case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
                         r_dcache_flush_count = 0;

trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -1100 +1100 @@
             else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV)
             {
-                if (sizeof(paddr_t) <= 32)
-                {
-                    assert(r_mmu_word_hi.read() == 0 &&
-                    "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
-                    r_icache_vci_paddr = (paddr_t) r_mmu_word_lo.read();
-                }
-                else
-                {
-                    r_icache_vci_paddr = (paddr_t) r_mmu_word_hi.read() << 32 |
-                                         (paddr_t) r_mmu_word_lo.read();
-                }
+                uint64_t pa = ((uint64_t)r_mmu_word_hi.read() << 32) |
+                              ((uint64_t)r_mmu_word_lo.read());
+
+                r_icache_vci_paddr = (paddr_t)pa;
                 r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
             }
@@ -2592 +2585 @@
 
                     case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
+                    {
+                        uint64_t pa = ((uint64_t)r_mmu_word_hi.read() << 32) |
+                                      ((uint64_t)r_mmu_word_lo.read());
+
+                        r_dcache_save_paddr = (paddr_t)pa;
                         r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
-                        if (sizeof(paddr_t) <= 32)
-                        {
-                            assert(r_mmu_word_hi.read() == 0 &&
-                            "high bits should be 0 for 32bit paddr");
-                            r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
-                        }
-                        else
-                        {
-                            r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 |
-                                                  (paddr_t)r_mmu_word_lo.read();
-                        }
                         break;
-
+                    }
                     case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
                         r_dcache_flush_count = 0;