Changeset 972 for trunk/platforms/tsar_generic_iob/arch.py

Timestamp:

Apr 11, 2015, 8:26:46 PM (9 years ago)

Author:

alain

Message:

Modify the tsar_generic_iob platform:
The vci_multi_dma component replicated in all cluster is replaced by a vci_mwmr_dma component.
This new component supports all hardware coprocessors respection the "coproc" interface.
Amongst the available coprocessors (defined in the SocLib? "coprocessor_components" directory)
the MWR_CPY coprocessor provide an improved memory copy service throughput x 2).

File:

• trunk/platforms/tsar_generic_iob/arch.py (modified) (10 diffs)

trunk/platforms/tsar_generic_iob/arch.py

@@ -19 +19 @@
 #
 #  All clusters contain (nb_procs) processors, one L2 cache, one XCU, and
-#  one DMA controller.
+#  one optional hardware coprocessor connected to a MWMR_DMA controller.
 #
 #  The "constructor" parameters (defined in Makefile) are:
@@ -27 +27 @@
 #  - nb_ttys        : number of TTY channels
 #  - fbf_width      : frame_buffer width = frame_buffer heigth
-#  - ioc_type       : can be 'BDV','HBA','SDC', but not 'RDK' 
-#
-#  The other hardware parameters (defined below) are:
+#  - ioc_type       : can be 'BDV','HBA','SDC', but not 'RDK'
+#   
+#
+#  The other hardware parameters (defined in this script) are:
 #  - nb_nics        : number of NIC channels
 #  - nb_cmas        : number of CMA channels
@@ -40 +41 @@
 #  - use_ramdisk    : use a ramdisk when True
 #  - vseg_increment : address increment for replicated vsegs
+#  - mwr_type       : coprocessor type / can be 'GCD','DCT','NOPE'
+#  - use_dma        : one single channel DMA per cluster if non zero
 #
 #  Regarding the boot and kernel vsegs mapping :
@@ -59 +62 @@
           nb_ttys   = 1,
           fbf_width = 128,
-          ioc_type  = 'BDV' ):
+          ioc_type  = 'HBA' ):
 
     ### define architecture constants
@@ -71 +74 @@
     p_width         = 4
     paddr_width     = 40
-    irq_per_proc    = 4          # NetBSD constraint
+    irq_per_proc    = 4          
     peri_increment  = 0x10000  
-
-    ### parameters checking
+    mwr_type        = 'CPY'
+
+    ### constructor parameters checking
 
     assert( nb_procs <= (1 << p_width) )
@@ -90 +94 @@
 
     assert( ioc_type in [ 'BDV' , 'HBA' , 'SDC' ] )
+
+    assert( mwr_type in [ 'GCD' , 'DCT' , 'CPY' , 'NONE' ] )
  
     ### define platform name
@@ -104 +110 @@
     xcu_size = 0x1000                      # 4 Kbytes
 
-    dma_base = 0x00B1000000
-    dma_size = 0x1000                      # 4 Kbytes 
+    mwr_base = 0x00B1000000
+    mwr_size = 0x1000                      # 4 Kbytes 
 
     mmc_base = 0x00B2000000
@@ -207 +213 @@
 
             ### components replicated in all clusters
-            ram = mapping.addRam( 'RAM', base = ram_base + offset, 
+            mapping.addRam( 'RAM', base = ram_base + offset, 
                                   size = ram_size )
-
-            mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, 
-                                     size = mmc_size, ptype = 'MMC' )
-
-            dma = mapping.addPeriph( 'DMA', base = dma_base + offset, 
-                                     size = dma_size, ptype = 'DMA', 
-                                     channels = nb_procs )
 
             xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, 
@@ -223 +222 @@
 
             mapping.addIrq( xcu, index = 0, isrtype = 'ISR_MMC' )
-
-            for i in xrange ( dma.channels ):
-                mapping.addIrq( xcu, index = 1+i, isrtype = 'ISR_DMA',
-                                channel = i )
+            mapping.addIrq( xcu, index = 1, isrtype = 'ISR_MWR' )
+
+            mapping.addPeriph( 'MMC', base = mmc_base + offset, 
+                                     size = mmc_size, ptype = 'MMC' )
+
+            if ( mwr_type == 'GCD' ):
+                mapping.addPeriph( 'MWR', base = mwr_base + offset,
+                                   size = mwr_size, ptype = 'MWR', subtype = 'GCD',
+                                   arg0 = 2, arg1 = 1, arg2 = 1, arg3 = 0 )  
+
+            if ( mwr_type == 'DCT' ):
+                mapping.addPeriph( 'MWR', base = mwr_base + offset,
+                                   size = mwr_size, ptype = 'MWR', subtype = 'DCT',
+                                   arg0 = 1, arg1 = 1, arg2 = 1, arg3 = 0 )  
+
+            if ( mwr_type == 'CPY' ):
+                mapping.addPeriph( 'MWR', base = mwr_base + offset,
+                                   size = mwr_size, ptype = 'MWR', subtype = 'CPY',
+                                   arg0 = 1, arg1 = 1, arg2 = 1, arg3 = 0 )  
 
             for p in xrange ( nb_procs ):
-                mapping.addProc( x, y, p )
+                mapping.addProc( x , y , p )
 
             ### external peripherals in cluster_io
@@ -406 +420 @@
                                local = False, big = False )
 
-            mapping.addGlobal( 'seg_dma_%d_%d' %(x,y), dma_base + offset, dma_size,
-                               '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'DMA',
-                               local = False, big = False )
-
             mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size,
                                '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC',
                                local = False, big = False )
+
+            if ( mwr_type != 'NONE' ):
+                mapping.addGlobal( 'seg_mwr_%d_%d' %(x,y), mwr_base + offset, mwr_size,
+                                   '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MWR',
+                                   local = False, big = False )
 
     return mapping