source: branches/v5

Revision Log Mode:


Legend:

Added
Modified
Copied or renamed
Diff Rev Age Author Log Message
(edit) @312   11 years cfuguet Updating width of the way index in DSPIN coherence flits. Using 2 bits …
(edit) @311   11 years cfuguet Including GET and SET methods for the FROM_L1_BC and FROM_MC_BC bit in …
(edit) @310   11 years cfuguet Introducing FROM_L1_BC and FROM_MC_BC in dspin param class to access …
(edit) @309   11 years joannou Bugfix : typo in component name (was 'dhcpp', is now 'dhccp')
(edit) @308   11 years cfuguet Fixing parameter name error in metadata of vci_mem_cache
(edit) @307   11 years cfuguet Including vci_mem_cache v5 using dspin interface for the coherence …
(edit) @306   11 years joannou Added tsar_mono_mmu and tsar_generic_mmu platforms
(edit) @305   11 years joannou In vci_mem_cache component: Adding an assert for cleanup commands …
(edit) @304   11 years joannou Bug fixing in vci_cc_vcache_wrapper component : - In TGT_RSP_DCACHE, …
(edit) @300   11 years joannou Moved tsar modules vci_cc_vcache_wrapper and vci_mem_cache under the …
(edit) @299   11 years alain bug fixing: coherence interrupt must be taken in the MISS_DIR_UPDT states.
(edit) @296   11 years alain introducing major modifications in vci_cc_vcache_wrappers - remove …
(add) @295   11 years cfuguet Introducing branches/v5/ components directory. This branch will be …
Note: See TracRevisionLog for help on using the revision log.