Timeline



Apr 14, 2010:

3:47 PM Changeset [25] by nipo
Uniformize 40 bit addresses
3:46 PM Changeset [24] by nipo
Remove loggers
3:46 PM Changeset [23] by nipo
Add non coherent platform
1:27 PM Changeset [22] by bouyer
Fix CPU address
7:12 AM Changeset [21] by nipo
Add DSX-based platform definition
5:27 AM Changeset [20] by nipo
Update DSX metadata

Apr 12, 2010:

12:58 PM Changeset [19] by guthmull
Fix uninitialized variable
12:41 AM Changeset [18] by gao
Bug correction

Apr 9, 2010:

1:37 PM Changeset [17] by simerabe
updating lib components
1:36 PM Changeset [16] by simerabe
updating lib components

Apr 8, 2010:

8:51 PM Changeset [15] by simerabe
changing broadcast parameters
6:07 PM Changeset [14] by simerabe
fixing bug related to broadcast
2:27 PM Changeset [13] by bouyer
Fix build with systemcass (add .read() on register access)
3:41 AM Changeset [12] by gao
bug correction

Apr 6, 2010:

11:38 AM Changeset [11] by simerabe
adding trace for debugging

Mar 30, 2010:

5:56 PM Changeset [10] by simerabe
changing broadcast offset on vci_ring_initiator
4:29 PM Changeset [9] by simerabe
updating multi-cluster platform
3:57 PM Changeset [8] by simerabe
new ring components for systemcass
1:08 PM Changeset [7] by guthmull
Fix same deadlock issue as in V4
12:32 PM WikiStart edited by nipo
(diff)
10:23 AM Changeset [6] by guthmull
Fix the deadlock also for SC requests

Mar 29, 2010:

6:13 PM Changeset [5] by guthmull
Fix a deadlock issue on the coherency network

Mar 26, 2010:

7:41 PM Changeset [4] by nipo
Forgot the vci_cc_vcache_wrapper2_multi
7:30 PM Changeset [3] by nipo
Import platforms
7:02 PM Changeset [2] by nipo
Import TSAR modules in TSAR's own svn
6:56 PM Changeset [1] by nipo
Create a directory for tsar modules
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