Timeline



Mar 18, 2013:

4:48 PM InterconnexionNetworks edited by alain
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4:33 PM InterconnexionNetworks edited by alain
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4:15 PM InterconnexionNetworks edited by alain
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3:54 PM Changeset [329] by joannou
Added test on INST/DATA for the CLACK in the …
3:51 PM InterconnexionNetworks edited by alain
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3:45 PM Changeset [328] by cfuguet
Including TYPE_CLEANUP_ACK_INST and TYPE_CLEANUP_ACK_DATA in the …

Mar 15, 2013:

2:26 PM WikiStart edited by meunier
Adding a Keywords section (diff)

Mar 14, 2013:

9:25 PM Changeset [327] by simerabe
introducing topcell examples using dspin ring interconnect
9:13 PM Changeset [326] by simerabe
introducing 2 new components : simple and local ring interconnect …
4:14 PM Changeset [325] by joannou
bugfix in vci_cc_vcache_wrapper_dspin_coherence : - consume fifo in …
2:41 PM Changeset [324] by joannou
updated the test_interrupt_delayslot : now testing for several delay values
10:59 AM Changeset [323] by joannou
removed unusefull flipflop r_*cache_cc_fifo_done + syntax correction …
9:52 AM Changeset [322] by cfuguet
Erasing binary generated files in tests_ccvcache_v4/test_sync from the repo

Mar 13, 2013:

6:17 PM Changeset [321] by joannou
bugfix in vci_cc_vcache_wrapper_dspin_coherence in coherence type checking
5:33 PM Changeset [320] by cfuguet
vci_mem_cache_dspin_coherence: - Fixing typo error in …
3:38 PM Changeset [319] by cfuguet
Fix bug in vci_mem_cache_dspin_coherence. The write signal in the …
3:12 PM Changeset [318] by joannou
vci_cc_vcache_wrapper_dspin_coherence now use DspinDhccpParam::* types …
2:53 PM Changeset [317] by cfuguet
Introducing missing debug strings in the vci_mem_cache cpp file
11:00 AM Changeset [316] by joannou
Introducing new tsar_mono_mmu_dspin_coherence platform Same as …
10:43 AM Changeset [315] by joannou
Introducing new dspin interface for …

Mar 12, 2013:

4:41 PM Changeset [314] by cfuguet
Erasing old comments in the reset.s file of the pre-loader
3:20 PM Changeset [313] by cfuguet
Erasing useless template parameters for the …

Mar 9, 2013:

1:03 AM Changeset [312] by cfuguet
Updating width of the way index in DSPIN coherence flits. Using 2 bits …
12:24 AM Changeset [311] by cfuguet
Including GET and SET methods for the FROM_L1_BC and FROM_MC_BC bit in …

Mar 8, 2013:

3:08 PM Changeset [310] by cfuguet
Introducing FROM_L1_BC and FROM_MC_BC in dspin param class to access …

Mar 6, 2013:

4:14 PM Changeset [309] by joannou
Bugfix : typo in component name (was 'dhcpp', is now 'dhccp')
3:12 PM Changeset [308] by cfuguet
Fixing parameter name error in metadata of vci_mem_cache
2:45 PM Changeset [307] by cfuguet
Including vci_mem_cache v5 using dspin interface for the coherence …

Feb 26, 2013:

6:28 PM Changeset [306] by joannou
Added tsar_mono_mmu and tsar_generic_mmu platforms
4:35 PM Changeset [305] by joannou
In vci_mem_cache component: Adding an assert for cleanup commands …
4:32 PM Changeset [304] by joannou
Bug fixing in vci_cc_vcache_wrapper component : - In TGT_RSP_DCACHE, …
4:19 PM Changeset [303] by joannou
Bug fix in generic_cache_tsar component : In the read_select function, …
9:19 AM Changeset [302] by cfuguet
Introducing IRQ_PER_PROC constant in the tsar boot loader …

Feb 19, 2013:

5:00 PM Changeset [301] by joannou
bugfix in vci_block_device_tsar_v4 : the component used a vci …
3:56 PM Changeset [300] by joannou
Moved tsar modules vci_cc_vcache_wrapper and vci_mem_cache under the …
1:07 PM Changeset [299] by alain
bug fixing: coherence interrupt must be taken in the MISS_DIR_UPDT states.
11:27 AM Changeset [298] by alain
Bug fixing in the NIC constructor
11:13 AM Changeset [297] by alain
Introducing the 3 states (EMPTY,VALID,ZOMBI) states in cache directory
11:00 AM Changeset [296] by alain
introducing major modifications in vci_cc_vcache_wrappers - remove …
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