Changes between Version 14 and Version 15 of AtomicOperations


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Timestamp:
Dec 7, 2015, 8:49:15 PM (7 years ago)
Author:
alain
Comment:

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  • AtomicOperations

    v14 v15  
    99 
    1010 * The '''CAS''' (Compare and Swap) operation is implemented as a specific VCI transaction. As there is no CAS instruction in the MIPS32 instruction set, this operation cannot be used by the software. It is only used by some hardware components such as the L1 cache controller (to allow the MMU to update the DIRTY bit in the page tables), or by some DMA peripheral such as the vci_mwmr_dma component (to atomically access the lock protecting a shared communication channel).
     11
     12For both types of operation, the addresses a supposed to be aligned on 32 bits word boundaries, and the data are supposed to be 32 bits words.
    1113
    1214== 2.  LL/SC operation ==
     
    9698== 3.  CAS operation ==
    9799
     100=== 3.1 general principle ===
    98101
    99 === 3.1 new semantic ===
     102The semantic of a CAS(X,D_old,D_new) transaction (three arguments in the VCI command) is the following:
    100103
    101 The formal semantic of a LL/SC access is :
    102 (1) The Store Conditional succeeds if there was no other Store Conditional at the same address since the last Linked Load.
     104 * If the value stored at address X is equal to the D_old value, the CAS returns a ''success'' code in the VCI response, and the value D_new is written at address X.
     105 * If the value stored at address X is not equal to the D_old value, the CAS returns a ''failure'' code in the VCI response, and no write is done at address X.
    103106
    104 The implemented semantic is :
    105 (2) The Store Conditional succeeds if the content of the memory has not changed since the last Linked Load.
     107=== 3.2 Implementation ===
    106108
    107 Clearly we have (1) => (2) . But we have only (2) => (1) when the software does not use the LL/SC mechanism to monitor WRITEs. Such use of the LL/SC mechanism has to be avoided.
     109This operation is implemented in the L2 cache controller.
    108110
    109 === 3.2 new protocol ===
    110 
    111 In the new protocol, there is no more LL on the network :
    112 
    113  * Linked Loads become simple Reads, where the data sent to the processor is recorded in a register of the L1 cache. When the processor issues a Store Conditional, the L1 cache sends a "SC" packet, where the first flits contain the data previously read and the next flits contain the data to write in the memory. So this new SC packet is 2 (32 bits accesses) or 4 flits (64 bits accesses) long.
    114 
    115  * The memory cache controller then compares the data read by the L1 cache to the data in the memory cache. If these two values are equal, the Store Conditional is done, and the response to the SC is success (0 value), else the Store Conditional is not done, and the response is failure (1 value).
    116 
    117 === 3.3 memory cache controller ===
    118 
    119 The memory cache controller does not have a linked access buffer any more. It simply has to be capable of recording pending Store Conditional in the table of transactions to the external RAM controller, in case of miss in the memory cache.
    120 
    121 The actions done by the memory cache controller for the various commands are described below :
    122 
    123 
    124 '''SC(SRCID, X)'''
    125 {{{
    126   Read the data in the memory cache.
    127   If ( data read by the L1 cache == data from the memory cache ) {
    128       - write data in the memory cache
    129       - send updates or invalidates to the owners of this cache line
    130       - after all responses to UPDATE or INVALIDATE have been received, return true
    131         to the L1 cache.   
    132   } else {
    133       return false to the L1 cache
    134   }
    135 }}}
    136 
    137 '''WRITE(SRCID, X)'''
    138 {{{
    139   - Scan the linked list of copies to send an UPDATE request
    140     to the L1 caches (other than SRCID)
    141   - Write data in the memory cache
    142   - after all responses to UPDATE have been received, acknowledge the
    143     write request.
    144 }}}
    145 
    146 '''READ(SRCID, X)'''
    147 {{{
    148   If ( cachable request ) {
    149     - register the SRCID in the list of copies associated to the X address.
    150     - return the complete or partial cache line
    151   } else {
    152     - return a single word.
    153   }
    154 }}}
    155 
    156 === 3.4  L1 cache controller ===
    157 
    158 The L1 cache controller receiving a new LL(X) request from the processor must locally register this request on the X address and the data sent to the processor. When it receives a SC(X) request from the processor, it checks the LL register and, if this register is valid, it sends a Store Conditional to the memory cache controller containing both the data read by the LL(X) and the data to write. This requires an extra register to store the address, the data, a VALID flip-flop, and a LONG flip-flop (in case of 64 bits LL/SC) in the L1 cache controller.
    159 
    160 The actions done by the L1 cache controller for the various commands are described below :
    161 
    162 '''LL(X) from processor'''
    163 {{{
    164   If (VALID = true & ADDRESS = X) {    // local spin-lock         
    165     return the read data to the processor
    166   } else {                                          // first LL access                       
    167     VALID <= true
    168     ADDRESS <= X
    169     DATA <= READ(X),
    170     and return the read value to the processor
    171   }
    172 }}}
    173 
    174 '''SC(X) from processor'''
    175 {{{
    176   If (VALID = true & ADDRESS = X)  {    // possible success
    177     send a SC(X) request to the memory cache containing the data stored in the LL register and the data to write,
    178     and return the Boolean response to the processor
    179     VALID <= false
    180   } else {                                         // failure 
    181    return a false value to the processor
    182    VALID <= false
    183   }
    184 }}}
    185 
    186 '''INVAL(L) or UPDATE(L) from memory controller'''
    187 {{{
    188   The LL register must not be invalidated.
    189   The L1 cache is updated or invalidated.
    190 }}}