Changes between Version 16 and Version 17 of AtomicOperations


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Timestamp:
Dec 8, 2015, 1:30:06 PM (7 years ago)
Author:
alain
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  • AtomicOperations

    v16 v17  
    55== 1.  Goals ==
    66
    7 The TSAR architecture implements two read-then-write atomic operations to support various synchronization mechanisms :
    8  * The '''LL/SC''' (Linked Load / Store Conditional) operation is implemented as two specific VCI transactions. As the LL/SC instructions are implemented in the MIPS32 instruction set, these instructions can be used by both the kernel code and by the application code to read a data at address X, test this data, and write the (possibly modified) data at the same address X, with the guaranty that no other access to this address was done between the read and write access.
     7The TSAR architecture implements two ''read-then-write'' atomic operations:
     8 * The '''LL/SC''' (Linked Load / Store Conditional) operation is implemented as two specific VCI transactions. As the LL/SC instructions are implemented in the MIPS32 instruction set, these instructions can be used by both the kernel code and by the application code to read a data at address X, test and modify this data, and write the modified data at the same address X, with the guaranty that no other access to this address was done between the read and the write access.
    99 
    10  * The '''CAS''' (Compare and Swap) operation is implemented as a specific VCI transaction. As there is no CAS instruction in the MIPS32 instruction set, this operation cannot be used by the software. It is only used by some hardware components such as the L1 cache controller (to allow the MMU to update the DIRTY bit in the page tables), or by some DMA peripheral such as the vci_mwmr_dma component (to atomically access the lock protecting a shared hardware/software communication channel).
     10 * The '''CAS''' (Compare and Swap) operation is implemented as a specific VCI transaction. As there is no CAS instruction in the MIPS32 instruction set, this operation is only used by some hardware components such as the L1 cache controller, or by some DMA peripheral controllers. 
    1111
    1212For both types of operation, the addresses a supposed to be aligned on 32 bits word boundaries, and the data are supposed to be 32 bits words.
     
    100100=== 3.1 general principle ===
    101101
    102 The semantic of a CAS(X,D_old,D_new) transaction (three arguments in the VCI command) is the following:
     102The semantic of the '''CAS(X,D_old,D_new)''' VCI transaction (three arguments in the VCI command) is the following:
    103103
    104104 * If the value stored at address X is equal to the D_old value, the CAS returns a ''success'' code in the VCI response, and the value D_new is written at address X.
    105105 * If the value stored at address X is not equal to the D_old value, the CAS returns a ''failure'' code in the VCI response, and no write is done at address X.
    106106
    107 === 3.2 Implementation ===
     107=== 3.2 Implementation and Usage ===
    108108
    109 This operation is implemented in the L2 cache controller.
    110 
     109This CAS operation is implemented in the L2 cache controller.
     110It is actually used by the MMU (Memory Management Unit) implemented in the L1 cache controller, to update the DIRTY bit in a page table entry.
     111It is also used by the vci_mwmr_dma component, to atomically access the lock protecting a shared hardware/software communication channel).
     112It cannot be directly used by the software.