Changes between Version 22 and Version 23 of AtomicOperations

Timestamp:

Dec 1, 2017, 1:01:49 PM (6 years ago)

Author:

alain

Comment:

--

AtomicOperations

@@ -15 +15 @@
 
 As we want to support commodity operating systems and existing software applications, any memory address can be the target of an atomic access.
-As the atomic access can be used to implement spin-locks, the address must be cacheable in order to benefit from the general coherence protocol, and avoid unnecessary transactions on the interconnection network.
+As the atomic access can be used to implement spin-locks, the address must be cacheable in order to benefit from the general coherence protocol, and avoid unnecessary transactions on the interconnection network. 
 
 === 2.1 General Principle ===
 
-From a conceptual point of view, the atomicity is handled on the memory controller side, that is actually the L2 cache controller in the TSAR architecture. Each L2 cache controller contains a list of all pending LL/SC atomic operations in an associative ''reservation table'', that contains 32 entries.
-
+From a conceptual point of view, the atomicity is handled on the memory controller side, that is actually the L2 cache controller in the TSAR architecture. Each L2 cache controller contains a list of all pending LL/SC atomic operations in an associative ''reservation table'', that contains 32 entries. Cette table doit enregistrer l'adresse X. Elle n'a pas besoin d'enregistrer le(s) numéro(s) des clients, mais elle doit identifier l'opération LL/SC pour éviter que deux opérations (LL/SC) à la même adresse X ne se mélangent.
  * When a processor P executes the LL(X) instruction for an address X, this réservation request is sent to the L2 cache by the L1 cache. The L2 cache allocates a 32 bits authentication key for this reservation. It registers both the X address and the K key in the associative ''reservation table'', and returns both the value stored at address X and the K value to the L1. Both the X address and the K key are also registered in the L1 cache. If another processor P' request a reservation for the same address X, it receives the saved K value from the L2 cache.