Changes between Version 6 and Version 7 of AtomicOperations


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Timestamp:
Jul 10, 2009, 10:34:21 AM (15 years ago)
Author:
choichil
Comment:

Some orthographic corrections

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  • AtomicOperations

    v6 v7  
    4343=== 3.1 memory cache controller ===
    4444
    45 The memory cache controller contains a dedicated storage that is used to register, for each cache line the set of  L1 caches that have copies. These sets of copies are implemented as linked lists of SRCIDs. To implement the Reservation Table, we just introduce, for each registered copy of a cache line, (i.e. each entry in this Reservation Table) one extra bit  to register a pending LL/SC atomic operation.
     45The memory cache controller contains a dedicated storage that is used to register, for each cache line the set of  L1 caches that have copies. These sets of copies are implemented as linked lists of SRCIDs. To implement the Reservation Table, we just introduce, for each registered copy of a cache line, (i.e. each entry in this Reservation Table) one extra bit to register a pending LL/SC atomic operation.
    4646This approach is scalable, but creates the possibility of “false conflicts”, when several atomic access are done to the same cache line.
    4747
     
    5959 }}}
    6060
    61 '''SC(SRCID, X)
     61'''SC(SRCID, X)'''
    6262{{{
    6363  Scan all copies associated to the cache line containing the X address
     
    9494=== 3.2  L1 cache controller ===
    9595
    96 The L1 cache controller receiving a  new LL(X) request from the processor must locally register this reservation on the X address to validate the use of the locally cached copy, and to check the address when it receives a SC(X) request from the processor. This requires an extra register to store the address, and a RESERVED flip-flop in the L1 cache controller.
     96The L1 cache controller receiving a new LL(X) request from the processor must locally register this reservation on the X address to validate the use of the locally cached copy, and to check the address when it receives a SC(X) request from the processor. This requires an extra register to store the address, and a RESERVED flip-flop in the L1 cache controller.
    9797
    9898The actions done by the L1 cache controller for the various commands are described below :
     
    112112'''SC(X) from processor'''
    113113{{{
    114   If (RESERVED = true & ADDRESS = X)  {    // possible succès
     114  If (RESERVED = true & ADDRESS = X)  {    // possible success
    115115    send a SC(X) request to the memory cache,
    116116    and return the Boolean response to the processor