Changes between Version 12 and Version 13 of CacheCoherence


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Timestamp:
Jun 8, 2010, 12:49:52 AM (14 years ago)
Author:
alain
Comment:

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  • CacheCoherence

    v12 v13  
    3434Reflecting the different behaviour of data & instruction caches, the "hybrid" cache coherence protocol DHCCP defines two different strategies,
    3535depending on the number of copies :
    36  * '''MULTICAST_UPDATE''' :  When the number of copies is smaller than the DHCCP threshold, the memory cache controller registers the locations
    37 of all the copies, and send a ''multicast_update'' transaction to each concerned L1 cache in case of modification.
    38  * '''BROADCAST_INVAL''' :  When the number of copies is larger than the DHCCP threshold, the memory cache controller registers only the number
    39 of copies (without localization) and send a ''broadcast_invalidate'' transaction  to all L1 caches in case of modication. 
     36 * '''MULTICAST_UPDATE''' :  When the number of copies is smaller than the DHCCP threshold, the memory cache controller registers the locations of all the copies, and send a ''multicast_update'' transaction to each concerned L1 cache in case of modification.
     37 * '''BROADCAST_INVAL''' :  When the number of copies is larger than the DHCCP threshold, the memory cache controller registers only the number of copies (without localization) and send a ''broadcast_invalidate'' transaction  to all L1 caches in case of modication. 
    4038
    4139== 2.  Types of transaction ==
     
    7169|| Cached Instruction   ||110||
    7270
    73  * A '''WRITE''' transaction can be a single word request or a variable length burst request. In case of burst, the VCI command packet contains at most 8 VCI flits, with consecutive addresses. All words belong to the same half cache line, and the VCI BE field can have different values for each flit (including the zero value). The VCI response packet contains one VCI flit. A WRITE burst transaction initiated by any DMA controller must respect the same 8 aligned words constraint. The VCI CMD field contains the VCI_WRITE code. The LSB bit of the PKTID field has the value 1. The other bits in the PKTID field can be used to code the slot index in the write buffer. If the modified cache line is replicated in one or several other L1 caches, the memory cache must guaranty that all copies have been
    74 updated or invalidated before the WRITE transaction is acknowledged.
     71 * A '''WRITE''' transaction can be a single word request or a variable length burst request. In case of burst, the VCI command packet contains at most 8 VCI flits, with consecutive addresses. All words belong to the same half cache line, and the VCI BE field can have different values for each flit (including the zero value). The VCI response packet contains one VCI flit. A WRITE burst transaction initiated by any DMA controller must respect the same 8 aligned words constraint. The VCI CMD field contains the VCI_WRITE code. The LSB bit of the PKTID field has the value 1. The other bits in the PKTID field can be used to code the slot index in the write buffer. If the modified cache line is replicated in one or several other L1 caches, the memory cache must guaranty that all copies have been updated or invalidated before the WRITE transaction is acknowledged.
    7572
    7673 * The TSAR architecture supports the '''LL/SC''' mechanism for atomic operations (see AtomicOperations).
     
    8481All these transactions are write transactions.
    8582 
    86  * A '''MULTI_UPDATE''' transaction is a multi-cast transaction sent by the memory cache controller when it receives a WRITE request to a replicated cache line and the number of copies does not exceeds the DHCCP threshold. It sends as many VCI transactions as the number of registered copies (but the writer). The VCI command packet contains (N+2) flits. The VCI ADDRESS field is constant and contains the address of the memory mapped UPDATE register in the L1 cache. The VCI CMD field contains the VCI_WRITE code. As the memory cache controller can handle several simultaneous update/invalidate transactions, the VCI PKTID field contains the transaction index. The VCI PLEN field contains the value  4*N, where N is the actual number of modified words in the cache line. The line index (34 bits) is transported in the VCI WDATA and VCI BE fields (the two LSB bits), of the first flit. The first modified word index (3 bits) is transported in the WDATA field of the second flit, and the N modified words in the WDATA and BE fields
    87 of the N following flits. For each modified word, the VCI BE field can have a different value (including the 0x0 value). The VCI response packet contains one single flit. The memory cache controller counts the number of VCI responses to detect the completion of the MULTICAST_UPDATE transaction.
     83 * A '''MULTI_UPDATE''' transaction is a multi-cast transaction sent by the memory cache controller when it receives a WRITE request to a replicated cache line and the number of copies does not exceeds the DHCCP threshold. It sends as many VCI transactions as the number of registered copies (but the writer). The VCI command packet contains (N+2) flits. The VCI ADDRESS field is constant and contains the address of the memory mapped UPDATE register in the L1 cache. The VCI CMD field contains the VCI_WRITE code. As the memory cache controller can handle several simultaneous update/invalidate transactions, the VCI PKTID field contains the transaction index. The VCI PLEN field contains the value  4*N, where N is the actual number of modified words in the cache line. The line index (34 bits) is transported in the VCI WDATA and VCI BE fields (the two LSB bits), of the first flit. The first modified word index (3 bits) is transported in the WDATA field of the second flit, and the N modified words in the WDATA and BE fields of the N following flits. For each modified word, the VCI BE field can have a different value (including the 0x0 value). The VCI response packet contains one single flit. The memory cache controller counts the number of VCI responses to detect the completion of the MULTICAST_UPDATE transaction.
    8884
    8985 * A '''MULTI_INVAL''' transaction is a multi-cast transaction, that is composed of several VCI transactions. When a memory cache makes a cache line replacement (following a MISS in the memory cache), and the victim line has a number of copies smaller than the DHCCP threshold, it sends as many VCI transactions as the number of registered copies. Both the VCI command packet and the VCI response packet contain only one flit. The VCI ADDRESS field contains the address of the memory mapped INVAL register in the L1 cache. The VCI CMD field contains the VCI_WRITE code. As the memory cache controller can handle several update/invalidate transactions simultaneously, the VCI PKTID field contains the transaction index.The VCI WDATA and VCI BE (the two LSB bits) fields contain the 34 bits line index. The memory cache controller counts the number of VCI responses to detect the completion of the  MULTI_INVAL transaction.