Changes between Version 15 and Version 16 of CacheCoherence


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Timestamp:
Jun 8, 2010, 2:03:56 PM (14 years ago)
Author:
alain
Comment:

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  • CacheCoherence

    v15 v16  
    6161The L1 cache controller can issue several simultaneous VCI transactions, that must be distinguished by the VCI TRDID field value. The VCI PKTID field is not used.
    6262
    63  * A '''READ''' transaction can be a single word request (in case of uncached access), or a burst, corresponding to a complete cache line (16 words). A READ burst transaction initiated by any DMA controller must respect the same 16 words cache line format. For all READ transaction, the VCI command packet contains one single VCI flit. The  VCI CMD field contains the VCI_READ code. The VCI PLEN field is used to define the burst length (number of bytes). A READ transaction has a type, encoded in the three LSB bits of the VCI PKTID field, and the the MSB bit must be 0.
     63 * A '''READ''' transaction can be a single word request (in case of uncached access), or a burst, corresponding to a complete cache line (16 words). A READ burst transaction initiated by any DMA controller must respect the same 16 words cache line format. For all READ transaction, the VCI command packet contains one single VCI flit. The  VCI CMD field contains the VCI_READ code. The VCI PLEN field is used to define the burst length (number of bytes). A READ transaction has a type, encoded in the two LSB bits of the VCI PKTID field, and the the MSB bit must be 0.
    6464
    6565|| TRDID for Uncached Data        ||0...00||