Changes between Version 18 and Version 19 of CacheCoherence


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Timestamp:
Jan 21, 2013, 4:24:22 PM (11 years ago)
Author:
alain
Comment:

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  • CacheCoherence

    v18 v19  
    4040
    4141Three types of transactions, have been identified :
    42  * Direct transactions : READ / WRITE / LL / SC
     42 * Direct transactions : READ / WRITE / LL / SC / CAS
    4343 * Coherence transactions : MULTI_UPDATE / MULTI_INVAL / BROADCAST_INVAL / CLEANUP
    4444 * External transactions : PUT / GET
    … …  
    5959the target is a memory cache controller, acting as a physical memory bank, or another VCI target peripheral. This target can be located in any cluster.
    6060
    61 The L1 cache controller can issue several simultaneous VCI transactions, that must be distinguished by the VCI TRDID field value. The VCI PKTID field is also used to distinguish transaction types.
     61The L1 cache controller can issue several simultaneous VCI transactions, that must be distinguished by the VCI TRDID and PKTID values.
    6262
    63  * A '''READ''' transaction can be a single word request (in case of uncached access), or a burst, corresponding to a complete cache line (16 words). A READ burst transaction initiated by any DMA controller must respect the same 16 words cache line format. For all READ transaction, the VCI command packet contains one single VCI flit. The  VCI CMD field contains the VCI_READ code. The VCI PLEN field is used to define the burst length (number of bytes). A READ transaction has a type, encoded in the three LSB bits of the VCI PKTID field (the MSB bit is ignored).
     63 * A '''READ''' transaction can have four sub-types: It can be instruction or data, and it can be cacheable or uncacheable. In case of a burst transaction the burst must be included in a 16 words cache line. This constraint applies for both the L1 cache controllers and the I/O controllers with a DMA capability. For all READ transaction, the VCI command packet contains one single VCI flit, and the VCI response packet contains at most 16 flits.
    6464
    65 || PKTID for Uncached Data        ||X000||
    66 || PKTID for Cached Data          ||X001||
    67 || PKTID for Uncached Instruction ||X010||
    68 || PKTID for Cached Instruction   ||X011||
     65 * A '''WRITE''' transaction can be a single word request or a variable length burst request. In case of burst, all words must belong to the same cache line. and the BE field can have different values for each flit (including the zero value). The VCI command packet contains at most 16 flits and the VCI response packet contains one VCI flit. A WRITE burst transaction initiated by a DMA controller must respect the same constraint.
    6966
    70  * A '''WRITE''' transaction can be a single word request or a variable length burst request. In case of burst, the VCI command packet contains at most 8 VCI flits, with consecutive addresses. All words belong to the same half cache line, and the VCI BE field can have different values for each flit (including the zero value). The VCI response packet contains one VCI flit. A WRITE burst transaction initiated by any DMA controller must respect the same 8 aligned words constraint. The VCI CMD field contains the VCI_WRITE code. The PKTID field contains the TYPE_WRITE code (X100, MSB bit is ignored). The TRDID field is used to code the slot index in the write buffer. If the modified cache line is replicated in one or several other L1 caches, the memory cache must guaranty that all copies have been updated or invalidated before the WRITE transaction is acknowledged.
     67 * A '''LL (Linked Load)''' transaction can target any single word contained in a memory cache. The response returns two 32 bits values that are the addressed data value, and a signature that has been allocated by the memory cache to this LL reservation. This means that the VCI command packet contains one flit and the VCI response packet contains two flits.
    7168
    72 || TRDID for Write burst       ||wbuf_index||
    73 || PKTID for Write burst       ||      X100||
     69 * A ''' SC (Store Conditionnal)''' transaction can target any single word contained in a memory cache. The command must transport both the new data value and the signature
     70obtained after the LL transaction. The response returns only a Boolean indicating failure/success for the SC transaction. This means that the VCI command packet contains two flits and the VCI response packet contains one flit.
    7471
    75  * The TSAR architecture supports the '''LL/SC''' mechanism for atomic operations (see AtomicOperations).
    76 For both a  LL (Linked Load) or a SC (Store Conditionnal) transaction, the VCI command packet and the VCI response packet contain one single VCI flit. The VCI CMD field must contain the VCI_LINKED_READ value (resp. VCI_STORE_CONDITIONNAL value). The VCI TRDID field takes the 0 value for all LL or SC packets.
     72 * A '''CAS (Compare & Swap)''' transaction can target any single word contained in a memory cache. The command must transport both the old data value and the new data value. The response returns only a Boolean indicating failure/success for the CAS transaction. This means that the VCI command packet contains two flits and the VCI response packet contains one flit.
    7773
    7874=== 2.2 Coherence transactions ===