Changes between Version 19 and Version 20 of InterconnexionNetworks
- Timestamp:
- Aug 29, 2010, 4:45:00 PM (14 years ago)
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InterconnexionNetworks
v19 v20 15 15 == 2. VCI initiators & targets indexing == 16 16 17 As a given hardware component can have several VCI ports (for example the L1 cache has t wo VCI initiator ports : one port to the direct network, and one port to the coherence network), each VCI port should - in principle - have a different identifier. In the specific case of the TSAR architecture, a VCI target or initiator component will never have several VCI port of the same type (Initiator type or Target type) on the same network. Therefore, each hardware component has – for sake of simplicity - an absoluteidentifier that is defined by three indexes :17 As a given hardware component can have several VCI ports (for example the L1 cache has three VCI ports : one initiator port to the direct network, one initiator port to the coherence network, and one target port on the coherence network), each VCI port has a different identifier that is defined by three indexes : 18 18 19 19 * '''X_ID''' is the cluster X-coordinate. … … 23 23 The X_ID, Y_ID and L_ID are coded on NX, NY, NL bits respectively. 24 24 NX, NY and NL are global parameters for the TSAR architecture, but NX & NY cannot be larger than 5 (no more than 1024 clusters), and NL cannot be larger than 4 25 (no more than 16 VCI hardware components per cluster).25 (no more than 16 ports per cluster). 26 26 27 In order to simplify the hardware implementation of the memory coherence protocol, the L_ID values are standardized for the memory cache and for the L1 caches : 27 In order to simplify the hardware implementation of the memory coherence protocol, the L_ID values are standardized on the coherence network, and the same value is used 28 for an initaitor port and for a target port: 28 29 29 30 ||COMPONENT ||LOCAL_INDEX|| 31 || || || 32 ||memory cache ||0000|| 33 ||Processor 1 (L1 cache) ||0001|| 34 ||Processor 2 (L1 cache) ||0011|| 35 ||Processor 3 (L1 cache) ||0101|| 36 ||Processor 4 (L1 cache) ||0111|| 30 ||COMPONENT ||LOCAL_INDEX|| 31 || || || 32 ||Processor 0 (L1 cache) ||0000 || 33 ||Processor 1 (L1 cache) ||0001 || 34 ||Processor 2 (L1 cache ||0010 || 35 ||Processor 3 (L1 cache) ||0011 || 36 ||Memory Cache ||0100 || 37 37 38 38 === 2.1 Target identification === … … 57 57 == 3. Direct Network & Coherence Network == 58 58 59 These two networks are implemented as two independent virtual networks, in the framework ofthe DSPIN network on chip general infrastructure :59 These two networks are implemented by the DSPIN network on chip general infrastructure : 60 60 61 61 * The '''local interconnect''' is implemented as two physically independent local rings, and the coherence ring supports a broadcast service for single flit VCI commands. 62 Note : These two physically independent rings willbe implemented later as one single physical ring supporting two virtual networks.62 Note : These two physically independent rings could be implemented later as one single physical ring supporting two virtual networks. 63 63 64 64 * The '''global interconnect''' is implemented as one DSPIN network, supporting two virtual sub-networks, and the coherence sub-network supports a broadcast service for single flit VCI commands. … … 74 74 * In a '''cleanup''' command packet from a L1 cache controller to a memory cache controller, the address is obtained by copying the (NX + NY) MSB bits of the line address in the VCI ADDRESS field (left aligned). The 0 value for the LADR address field is used to select the memory cache. 75 75 76 * In a '''broadcast_invalidate''' command packet, the ADDRESS[1:0] bits must be equal to 0x3. The 20 bits ADDRESS[21:2] will be used in a future extension of the DSPIN network to define the bounding box of a limited broadcast 76 * In a '''broadcast_invalidate''' command packet, from a memory cache controller to a L1 cache controller, the ADDRESS[1:0] bits must be equal to 0x3. The 20 bits ADDRESS[39:20] contain the XMIN,XMAX,YMIN,YMAX values defining the bounding box of the broadcast: 77 78 || XMIN || XMAX || YMIN || YMAX || RESERVED ||11|| 79 || 5 || 5 || 5 || 5 || 18 || 2|| 77 80 78 81 === 3.2 VCI parameters === … … 80 83 All Hardware components connected to the direct network or to the coherence network respect the VCI/OCP communication interface. 81 84 82 The direct network, and the coherence network being ''time-multiplexed'' on the DSPIN infrastructure, have identical VCI parameters :85 The direct network, and the coherence network being ''time-multiplexed'' on the DSPIN infrastructure, have identical VCI formats : 83 86 84 87 || VCI Field || width || 85 || ||||86 ||ADDRESS || 40 bits ||87 ||WDATA , RDATA || 32 bits ||88 ||PLEN || 8bits ||89 ||SRCID, RSRCID || 14 bits ||90 ||TRDID, RTRDID || 4 bits||91 ||PKTID, RPKTID || 4 bits||92 ||RERROR || 2 bits||88 || || || 89 ||ADDRESS || 40 bits || 90 ||WDATA , RDATA || 32 bits || 91 ||PLEN || 8 bits || 92 ||SRCID, RSRCID || 14 bits || 93 ||TRDID, RTRDID || 4 bits || 94 ||PKTID, RPKTID || 4 bits || 95 ||RERROR || 2 bits || 93 96 94 97 The TSAR architecture uses three values for the VCI RERROR field, in order to simplify the VCI/DSPIN wrapper, and to reduce the DSPIN Write Response packet length to one flit :
