Changes between Version 35 and Version 36 of InterconnexionNetworks

Timestamp:

Jun 1, 2011, 4:41:10 PM (13 years ago)

Author:

alain

Comment:

--

InterconnexionNetworks

@@ -27 +27 @@
 but can be smaller, if the number of clusters is smaller than 1024. NL is equal to 4 (no more than 16 target ports or 16 initiator ports per cluster).
 
-In order to simplify the hardware implementation of the memory coherence protocol, the L_ID values are standardized on the coherence network, and the same value is used for an initaitor port and for a target port: If the number of processors per cluster is NPROCS, the processor L_ID value is between 0 and (NPROCS-1).  The memory cache L_ID is equal to NPROCS.
+In order to simplify the hardware implementation of the memory coherence protocol, the L_ID values are standardized on the coherence network, and the same value is used for an initiator port and for a target port: If the number of processors per cluster is NPROCS, the processor L_ID value is between 0 and (NPROCS-1).  The memory cache L_ID is equal to NPROCS.
 
 
@@ -64 +64 @@
 On the direct network, the addresses and data are controlled by the software.
 
-=== 3.2  VCI Address generation on the coherence network ===
+=== 3.2  VCI Address & data on the coherence network ===
 
 On the coherence network, the addresses and data are defined by the hardware with the following policy:
 
-For all command packets (update, invalidate, and cleanup), the line index (up to 34 bits if we use 40 bits adresses) is transported in the WDATA and BE fields of the first VCI flit. The WDATA field contains the 32 LSB bits of the line index, and the BE field contain the 2 MSB bits of the line index. The multicast invalidate, broadcast invalidate, and cleanup packets contain one single VCI flit. The multi-cast update packets contain (2+N) flits : the WDATA field of the second flit contains the index of the first word to be updated in the cache line. The following flits (at most 16 flits) contains the values to be written.
+For all command packets (multi-update, multi-invalidate, broadcast-invalidate, and cleanup), the VCI CMD field is a WRITE. The line index (up to 34 bits if we use 40 bits addresses) is transported in the WDATA and BE fields of the first VCI flit. The WDATA field contains the 32 LSB bits of the line index, and the BE field contain the 2 MSB bits of the line index. The multicast invalidate, broadcast invalidate, and cleanup packets contain one single VCI flit. The multi-cast update packets contain (2+N) flits : the WDATA field of the second flit contains the index of the first word to be updated in the cache line. The following flits (at most 16 flits) contains the values to be written.
 
  * In a '''multicast''' command packet from a memory cache controller to a L1 cache controller, the address is obtained by copying the target L1 cache SRCID in the MSB bits of the VCI ADDRESS (left aligned) : The L1 cache L_ID is actually used as the LADR address field. UPDATE/INVAL requests are distinguished by the bit ADDRESS[3] (0 for INVAL, 1 for UPDATE). DATA/INSTRUCTION caches are distinguished by the bit ADDRESS[2] (0 for DATA, 1 for INSTRUCTION). 
 
- * In a '''cleanup''' command packet from a L1 cache controller to a memory cache controller, the address is obtained by copying the (NX + NY) MSB bits of the line address in the VCI ADDRESS field (left aligned). The 0 value for the LADR address field is used to select the memory cache.
+ * In a '''cleanup''' command packet from a L1 cache controller to a memory cache controller, the address is obtained by copying the (NX + NY) MSB bits of the line index in the VCI ADDRESS field (left aligned). The NPROCS value for the LADR address field is used to select the memory cache.
 
  * In a '''broadcast_invalidate''' command packet, from a memory cache controller to a L1 cache controller, the  ADDRESS[1:0] bits must be equal to 0x3. The 20 bits ADDRESS[39:20]  contain the XMIN,XMAX,YMIN,YMAX values defining the bounding box of the broadcast: