Changes between Version 47 and Version 48 of InterconnexionNetworks

Timestamp:

Mar 19, 2013, 12:57:33 PM (11 years ago)

Author:

alain

Comment:

--

InterconnexionNetworks

@@ -11 +11 @@
  * The '''Coherence Network''' is used to transport the coherence packets implementing the DHCCP coherence protocol between L2 cache controllers and L1 cache controllers. This network is not visible by the software, and does not use wrappers, as the L1 and L2 cache controllers use directly the DSPIN packet format. Here again there is two physically separated networks to transport L2-to-L1 packets, and to transport L1-to-L2 packets. Both networks have a two-level hierarchical structure with a local interconnect in each cluster (that can be implemented as a local crossbar, or as a local ring), and a global interconnect (implemented as a 2D mesh).
 
- * The '''Direct Network''' and the '''coherence Network''' are physically separated in each cluster, but 
-they are only logically separated for the global communications: Regarding the local interconnect, there is four physically separated local crossbars (or local ring) transporting the ''direct command'', ''direct response'', '' coherence L1-to-L2'', ''coherence L2-to-L1'' packets.  Regarding the global interconnect, the DSPIN infrastructure supporting virtual channels, the ''direct command'' and the ''coherence L2-to-L1" packets are multiplexed on the same 2D mesh (40 bits DSPIN flit width). Similarly, the ''direct response'' and ''coherence L1-to-L2'' packets are multiplexed on the same 2D mesh (33 bits DSPIN width).
+ * The '''Direct Network''' and the '''coherence Network''' are physically separated in each cluster, but they are only logically separated for the global communications: Regarding the local interconnect, there is four physically separated local crossbars (or local ring) transporting the ''direct command'', ''direct response'', '' coherence L1-to-L2'', ''coherence L2-to-L1'' packets.  Regarding the global interconnect, the DSPIN infrastructure supporting virtual channels, the ''direct command'' and the ''coherence L2-to-L1" packets are multiplexed on the same 2D mesh (40 bits DSPIN flit width). Similarly, the ''direct response'' and ''coherence L1-to-L2'' packets are multiplexed on the same 2D mesh (33 bits DSPIN width).
 
  * The '''External Network''' supports communications between the L2 caches and the ''tiles'' implementing the 3D L3 cache, in case of MISS or cache line replacement in the L2 caches. It has a 3D mesh topology and the DSPIN flit width is 64 bits. This external network addressing space is not visible by the software.