Changes between Version 5 and Version 6 of Specification

Timestamp:

Sep 5, 2012, 7:10:23 PM (12 years ago)

Author:

alain

Comment:

--

Specification

@@ -3 +3 @@
 = TSAR architecture overview =
 
-The TSAR shared memory architecture is a scalable, cache coherent, general-purpose multicore architecture. It is intended to support commodity applications and operating systems running on standard PCs, such as LINUX or FreeBSD. Therefore, the cache coherence must be entirely guaranteed by the hardware. Moreover, the TSAR architecture must provide hardware support for a paginated virtual memory and efficient atomic operations for synchronization.
+The TSAR shared memory architecture is a scalable, cache coherent, general-purpose multicore architecture. It is intended to support commodity applications and operating systems running on standard PCs, such as LINUX or NetBSD. Therefore, the cache coherence must be entirely guaranteed by the hardware. Moreover, the TSAR architecture provides a paginated virtual memory and efficient atomic operations for synchronization.
 
-The main technical issue is the scalability, as this architecture is intended to integrate up to 4096 cores (even if the first prototype will contain only 16 cores). The second technical issue is the power consumption, and all technical choices described below are driven by these two goals.
+The main technical issue is the scalability, as this architecture is intended to integrate up to 4096 cores (even if the first prototype will contain only 128 cores). The second technical issue is the power consumption, and all technical choices described below are driven by these two goals.
 
 == 1. Processor core == 
 
-In order to obtain the best MIPS/MicroWatt ratio, the TSAR processor core is a simple 32 bits, single instruction issue RISC processor, with no superscalar features, no out of order execution, no branch prediction, no speculative execution. In order to avoid the enormous effort to develop a brand new compiler, TSAR will use an existing processor core. The choice is not important : It could be a MIPS32, a PPC405, a SPARC V8, or an ARM7 core, as all these processor cores have similar performances.
-
-The first TSAR architecture demonstrator will use a MIPS32 processor core.
+In order to obtain the best MIPS/MicroWatt ratio, the TSAR processor core is a simple 32 bits, single instruction issue RISC processor, with no superscalar features, no out of order execution, no branch prediction, no speculative execution. In order to avoid the enormous effort to develop a brand new compiler, TSAR uses an existing processor core: The first TSAR prototype contains a MIPS32 processor core. This choice is not important : It could be as well a PPC405, a SPARC V8, or an ARM7 core, as all these processor cores have similar performances.
 
 == 2. Memory layout ==
 
 The physical address space size is a parameter. The maximal value is 1 Tbytes (40 bits physical address). For scalability reasons, the TSAR physical memory is logically shared, but physically distributed : The architecture is clusterized , and has a 2D mesh topology. Each cluster contains up to 4 processors, a local interconnect and one physical memory bank. The architecture is NUMA (Non Uniform Memory Access) : All processors can access all memory banks, but the access time, and the power consumption depend on the distance between the processor and the memory bank.
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-
 
 Each memory bank is actually implemented as a memory cache :  A memory cache is not a classical level 2 cache. The physical address space is statically split into fixed size segments, and each memory cache is responsible for one segment, defined by the physical address MSB bits. With this principle, it is possible to control the physical placement of the data by controlling the address values.