Changes between Initial Version and Version 1 of VirtualMemory

Timestamp:

Jun 27, 2009, 2:41:36 PM (15 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ +1 @@
+[[outline]]
+
+= TSAR virtual memory =
+
+The TSAR MMU can be used with any 32 bits, single instruction issue, processor.
+In order to be independent on the processor core choice, the TLB MISS are handled by an hardwired Finite State Machine (called a Table Walk), without software action.  
+
+== 1. Page Table Organisation ==
+
+The TSAR virtual memory uses a paged approach. The TSAR architecture defines two page sizes :
+-       4 Kbytes pages
+-       2 Mbytes pages
+The virtual address space size is 4 Gbytes (32 bits virtual addresses). 
+The physical address space is limited to 1 Tbytes (40 bits physical addresses). 
+
+The page table are build by the operating system, and are stored in memory. They are used for both the VPN (Virtual Page number)  to PPN (Physical Page Number) translation, and for access rights checking.
+
+=== 1.1 Two levels structure ===
+
+As described below, the Page Table has a hierarchical two levels structure : 
+
+
+
+The general mapping constraints are the following
+-       All page tables (first & second level) must be aligned : the page table base adress must be a multiple of 8K bytes for a first level page table, and multiple of 4K bytes for a second level page table.
+-       The page tables can be placed anywhere in the physical address space.
+-       The PTPR register (located in the generic MMU, and initialised by  the OS at each context switch) contains actually the 26 MSB bits  of the first level page table base address. It must be extended (left-shifted) to 36 bits by the hardware.
+
+=== 1.2 Second Level Page Table Entry Format ===
+
+Each entry in a second level page table is a 64 bits word containing a 4K bytes page descriptor (Called PTE2) :
+
+
+
+PPN2    Physical Page Number    Concatened to the page offset to build the 40 bits address
+V       Valid entry     Valid entry when 1 (set by the OS)
+T       entry Type      Must be 0 for a PTE2 (set by the OS)
+L       Local access    Used by the OS for page replacement (set by the hardware)
+R       Remote access   Used by the OS for page replacement (set by the hardware)
+C       Cachable        The page is cachable in the L1 cache when 1 (set by the OS)
+W       Writable        The page is writable when 1 (set by the OS)
+X       eXecutable      The page can contain instructions when 1 (set by the OS)
+U       User    The page accessible in user mode when 1 (set by the OS)
+G       Global  Entry not invalidated in TLB flush when 1 (set by the OS)
+D       Dirty   The page has been modified when 1 (set by the hardware)
+
+
+The L, R, D bits are used by the operating system to implement the page replacement policy. The D bit is set by the hardware, when a page is written and when it is not already set, using an atomic access (LL/SC).
+The L & R bits are set by the hardware, when the page is accessed after a TLB miss, and when it is not already set, using an atomic access (LL/SC).
+
+=== 1.3 First Level Page Table Entry Format ===
+
+Each entry in a first level page table is a 32 bits word containing either a 2M bytes page descriptor (called PTE1), or a second level  page table descriptor (called PTD1) :
+
+
+
+
+
+
+
+
+
+
+If the entry is a PTE1, the PPN1 value (19 bits) must be concatened with the page offset (21 bits) to build the 40 bits physical address. The (V, T, L, R, C, W, X, U, G, D) bits have the same meaning as in a PTE2. 
+
+If the entry is a PTD1, PTBA is the Page Table Base Address. The PTBA value (28 bits) must be left-shifted by 12 bits to define the base address of the level 2 page table. The page table being aligned in memory, the 12 LSB bits of this address have a 0 value. 
+
+== 2. Generic MMU ==
+
+For each TSAR programmable processor, the generic MMU is implemented as an hardware component in the L1 cache controller. As the processor core can issue two simultaneous instruction and data requests, there is actually two separated hardware MMUs for instruction and data. Each MMU contains a TLB (Translation Look-aside Buffer).
+These TLBs are implemented as set-associative caches containing 64 entries (8 sets of 8 ways). Each TLB contains a mix of 4Kbytes and 2 Mbytes page descriptors.
+
+for 4 Kbytes & 4 Mbytes pages. 
+
+== 3. I/O MMU ==
+
+To be defined...
+