Changes between Version 11 and Version 12 of VirtualMemory


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Timestamp:
Jun 29, 2009, 11:09:30 AM (13 years ago)
Author:
alain
Comment:

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  • VirtualMemory

    v11 v12  
    110110
    111111Similarly, the L1 cache controller contains two separated hardware MMUs for instruction and data. Each MMU contains a 64 entries TLB (Translation Look-aside Buffer).
    112 These TLBs are implemented as set-associative caches (8 sets of 8 ways). Each entry in these TLBs can contain either a 4 Kbytes page descriptor, or a 2 Mbytes page descriptor.
     112These TLBs are implemented as set-associative caches (16 sets of 4 ways). Each entry in these TLBs can contain either a 4 Kbytes page descriptor, or a 2 Mbytes page descriptor.
    113113
    114 For both data & instructions, the TSAR L1 caches use physical addresses (the tags contained in the directories are obtained from the physical addresses).
    115 The access to the L1 cache being a critical path, the TSAR MMU use a speculative approach to avoid to serialize the TLB access and the L1 cache access.
     114[[Image(cache_tlb.png, nolink)]]
     115
     116For both data & instructions, the TSAR L1 caches use physical addresses : the cache directories are indexed by the physical addresses, and the tags contained in the directories are obtained from the physical addresses. The access to the L1 cache being a critical path, the TSAR MMU use a speculative approach to avoid to serialize the TLB access and the L1 cache access:
     117 * After each TLB hit, the input VPN and the resulting PPN values are saved in two VPN_save & PPN_save registers.
     118 * During access (n), the PPN_save value, corresponding to access (n_1) is used to access the cache. Simultaneously, the cache controller checks that the VPN value is equal to the VPN_save value (no page change).
     119 * In case of TLB hit with a page change, the cache must be accessed twice, which means one cycle penalty.
     120
    116121
    117122=== 2.1 Generic MMU activation ===