Changes between Version 18 and Version 19 of VirtualMemory


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Timestamp:
Jul 1, 2009, 4:59:59 PM (15 years ago)
Author:
alain
Comment:

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  • VirtualMemory

    v18 v19  
    11[[PageOutline]]
    22
    3 = TSAR virtual memory =
     3= TSAR MMU =
    44
    5 The TSAR MMU (Memory Management Unit) is an hardware component implemented in the L1 cache controller. This cache controller is a generic component that can be used with any  single instruction issue, 32 bits processor. As any MMU, the generic TSAR MMU is in charge of the virtual to physical address translation, and perfoms
    6 access right verifications. It implements a paginated virtual memory, supporting two page sizes : 4 Kbytes pages, and 2 Mbytes pages.
     5The TSAR MMU (Memory Management Unit) is an hardware component implemented in the L1 cache controller. This generic component can be used with any  single instruction issue, 32 bits processor.
    76
    87[[Image(generic_mmu.png, nolink)]]
     
    109As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches,
    1110sharing the same physical access to the VCI/OCP interconnect. These L1 caches use physical addresses.
    12 Similarly, the L1 cache controller contains two separated hardware MMUs for instruction and data. 
     11As any MMU, the generic TSAR MMU is in charge of the virtual to physical address translation, and perfoms
     12access right verifications. It implements a paginated virtual memory, supporting two page sizes : 4 Kbytes pages, and 2 Mbytes pages.
     13Therefore, the TSAR MMU contains two separated hardware TLBs for instruction and data. 
    1314In order to be independent on the processor core choice, the TLB MISS are handled by an hardwired Finite State Machine (called a Table Walk), without any software action. 
    1415
     
    100101
    101102
    102 == 2. Generic MMU ==
     103== 2. Generic MMU architecture ==
    103104
    104105The generic MMU is implemented as an hardware component in the L1 cache controller.
     
    178179|| MMU_DBVAR                 ||  14      || Data Bad Virtual Address Register             || R      ||
    179180
    180 
    181 
    182 
    183181== 3. I/O MMU ==
    184182