Changes between Version 1 and Version 2 of VirtualMemory


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Timestamp:
Jun 27, 2009, 3:06:15 PM (15 years ago)
Author:
alain
Comment:

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  • VirtualMemory

    v1 v2  
    1 [[outline]]
     1[[PageOutline]]
    22
    33= TSAR virtual memory =
    … …  
    3131Each entry in a second level page table is a 64 bits word containing a 4K bytes page descriptor (Called PTE2) :
    3232
     33 * PTE2[31:0] :
     34||V||T||L||R||C||W||X||U||flLL||D||              22 bits reserved         ||
    3335
     36 * PTE2[63:32] :
     37|| reserved ||            PPN2 (28 bits)                  ||
    3438
    35 PPN2    Physical Page Number    Concatened to the page offset to build the 40 bits address
    36 V       Valid entry     Valid entry when 1 (set by the OS)
    37 T       entry Type      Must be 0 for a PTE2 (set by the OS)
    38 L       Local access    Used by the OS for page replacement (set by the hardware)
    39 R       Remote access   Used by the OS for page replacement (set by the hardware)
    40 C       Cachable        The page is cachable in the L1 cache when 1 (set by the OS)
    41 W       Writable        The page is writable when 1 (set by the OS)
    42 X       eXecutable      The page can contain instructions when 1 (set by the OS)
    43 U       User    The page accessible in user mode when 1 (set by the OS)
    44 G       Global  Entry not invalidated in TLB flush when 1 (set by the OS)
    45 D       Dirty   The page has been modified when 1 (set by the hardware)
     39The PTE2 fields are defined as follows :
     40 
     41|| PPN2 || Physical Page Number  || 28 bits : Concatened to the page offset to build the 40 bits address ||
     42|| V            || Valid bit                          || Valid entry when 1 (set by the OS) ||
     43|| T            || Type bit                        || PTD when 1 / Must be 0 for a PTE2 (set by the OS) ||
     44|| L            || Local access bit             || Used by the OS for page replacement (set by the hardware) ||
     45|| R            || Remote access        bit        || Used by the OS for page replacement (set by the hardware) ||
     46|| C            || Cachable bit                   || The page is cachable in the L1 cache when 1 (set by the OS) ||
     47|| W            || Writable bit                     || The page is writable when 1 (set by the OS) ||
     48|| X            || eXecutable bit               || The page can contain instructions when 1 (set by the OS) ||
     49|| U            || User bit                           || The page is accessible in user mode when 1 (set by the OS) ||
     50|| G            || Global       bit                        || Entry not invalidated in TLB flush when 1 (set by the OS) ||
     51|| D            || Dirty bit                          || The page has been modified when 1 (set by the hardware) ||
    4652
    4753