Changes between Version 19 and Version 20 of VirtualMemory

Timestamp:

Jul 2, 2009, 4:29:36 PM (15 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -4 +4 @@
 
 The TSAR MMU (Memory Management Unit) is an hardware component implemented in the L1 cache controller. This generic component can be used with any  single instruction issue, 32 bits processor. 
-
-[[Image(generic_mmu.png, nolink)]]
 
 As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches,
@@ -13 +11 @@
 Therefore, the TSAR MMU contains two separated hardware TLBs for instruction and data.  
 In order to be independent on the processor core choice, the TLB MISS are handled by an hardwired Finite State Machine (called a Table Walk), without any software action.  
+
+[[Image(generic_mmu.png, nolink)]]
 
 == 1. Page Table Organisation ==