Changes between Version 35 and Version 36 of VirtualMemory

Timestamp:

Sep 11, 2009, 1:44:10 PM (15 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -245 +245 @@
 
 
-=== 3.3 generic MMU registers mapping ===
-
-The generic MMU contains a set of registers (or pseudo-registers) that can be accessed by operating system,
+=== 3.3 generic MMU registers format & mapping ===
+
+The generic MMU contains a set of 32 bits registers (or pseudo-registers) that can be accessed by operating system,
 through a dedicated MMU driver.
 In the case of the MIPS processor, these registers are implemented in coprocessor 2, and are accessed 
@@ -271 +271 @@
 || MMU_IBVAR                          ||  13      || Instruction Bad Virtual Address Register  || R      ||
 || MMU_DBVAR                        ||  14      || Data Bad Virtual Address Register             || R      || 
-|| MMU_PARAMS                      ||  14      || Caches & TLBs hardware parameters        || R      || 
-
-The MMU_MODE register has four bits and these 16 values are described as below :
+|| MMU_PARAMS                      ||  15      || Caches & TLBs hardware parameters        || R      || 
+|| MMU_RELEASE                      ||  16      || Generic MMU release number                    || R      ||
+
+The '''MMU_PTPR''' register contains the base address of the currently used first level page table.
+As this base address is aligned on a 8 Kbytes boundary, and we want to support (up to) 40 bits
+physical addresses, the PTPR register contains only the 27 MSB bits of the base address :
+
+|| 00000 || BASE_ADDRESS[39:13] ||
+
+The '''MMU_MODE''' register has four bits and these 16 values are described as below :
 
 ||   MODE3   ||    MODE2   ||     MODE1   ||     MODE0    ||    description                                                                     ||
@@ -295 +302 @@
 ||     1     ||      1     ||      1      ||       1      || TLBs and caches actived                                                            ||
 
-The MMU_PARAMS register define the instruction and data caches & TLBs characteristics:
-  ||NWAYS_TLB_D||NSETS_TLB_D||NWAYS_CAHE_D||NSETS_CACHE_D||NWAYS_TLB_I||NSETS_TLB_I||NWAYS_CAHE_I||NSETS_CACHE_I||NWORDS||
- * NWAYS_TLB (3 bits) : Ln(number of associative ways for the TLB)
- * NSETS_TLB (4 bits) : Ln(number of associative ways for the TLB)
- * NWAYS_CACHE = Ln(number of associative ways for the TLB)
- * NSETS_CACHE (4 bits) : Ln(number of associative ways for the TLB)
- * NWORDS_CACHE Ln(number of associative ways for the TLB)
+The '''MMU_PARAMS''' register define the instruction and data caches & TLBs characteristics :
+
+  ||WTD||STD||WCD||SCD||WTI||STI||WCII||SCI||NBL||
+ * WTD (3 bits) : Ln(number of associative ways for the Data TLB)
+ * STD (4 bits) : Ln(number of sets for the Data TLB)
+ * WCD (3 bits) : Ln(number of associative ways for the Data Cache)
+ * SCD (4 bits) : Ln(number of sets ways for the Data Cache)
+ * WTI (3 bits) : Ln(number of associative ways for the Instruction TLB)
+ * STI (4 bits) : Ln(number of sets for the Instruction TLB)
+ * WCI (3 bits) : Ln(number of associative ways for the Instruction Cache)
+ * SCI (4 bits) : Ln(number of sets ways for the Instruction Cache)
+ * NBL (4 bits) : Ln(number of bytes per Data or Instruction cache line)
+
+The '''MMU_RELEASE''' register contains the release number for a given hardware implementation :
+|| SPECIFICATION_INDEX || IMPLEMENTATION_INDEX ||
+ * SPECIFICATION_INDEX (16 bits)
+ * IMPLEMENTATION_INDEX (16 bits)