Changes between Version 4 and Version 5 of VirtualMemory


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Timestamp:
Jun 27, 2009, 4:25:11 PM (13 years ago)
Author:
alain
Comment:

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  • VirtualMemory

    v4 v5  
    1616The page table are build by the operating system, and are stored in memory. They are used for both the VPN (Virtual Page number)  to PPN (Physical Page Number) translation, and for access rights checking.
    1717
    18 === 1.1 Two levels structure ===
     18=== 1.1 Two levels Page Table structure ===
    1919
    2020As described below, the Page Table has a hierarchical two levels structure :
     
    100100
    101101For each TSAR programmable processor, the generic MMU is implemented as an hardware component in the L1 cache controller. As the processor core can issue two simultaneous instruction and data requests, there is actually two separated hardware MMUs for instruction and data. Each MMU contains a TLB (Translation Look-aside Buffer).
    102 These TLBs are implemented as set-associative caches containing 64 entries (8 sets of 8 ways). Each TLB contains a mix of 4Kbytes and 2 Mbytes page descriptors.
     102These TLBs are implemented as set-associative caches containing 64 entries (8 sets of 8 ways). Each entry in these TLBs can contain either a 4 Kbytes page descriptor, or a 2 Mbytes page descriptor.
    103103
    104 for 4 Kbytes & 4 Mbytes pages.
     104For both data & instructions, the TSAR L1 caches use physical addresses (the tags contained in the directories are obtained from the physical addresses).
     105The access to the L1 cache being a critical path, the TSAR MMU use a speculative approach to avoid to serialize the TLB access and the L1 cache access.
     106
     107=== 2.1 Generic MMU activation
     108
     109After general RESET the generic MMU is desactivated : As long as the MMU is not activated, the 32 bits virtual address is simply extended to 40 bits,
     110 and directly used as a physical address. The instruction MMU and the data MMU can be separately activated by the software, by writing in
     111
     112=== 2.2 Generic MMU exceptions ===
     113
     114=== 2.1 generic MMU registers mapping ===
     115
     116The following registers are the  by appending
     117
     118
    105119
    106120== 3. I/O MMU ==