Changes between Version 54 and Version 55 of VirtualMemory


Ignore:
Timestamp:
Oct 16, 2014, 10:31:02 AM (8 years ago)
Author:
cfuguet
Comment:

Updating MMU registers. Especifically, the physical address extension registers were missing

Legend:

Unmodified
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Modified
  • VirtualMemory

    v54 v55  
    283283|| MMU_DCACHE_PA_INVAL ||   20   || Data cache inval physical address           || W    ||
    284284|| MMU_LL_RESET        ||   21   || LLSC reservation buffer invalidation        || W    ||
     285|| MMU_DOUBLE_LL       ||   22   || 64 bits linked-load transaction             || W    ||
     286|| MMU_DOUBLE_SC       ||   23   || 64 bits store-conditional transaction       || W    ||
     287|| MMU_DATA_PADDR_EXT  ||   24   || Physical address extension for data access  || W    ||
     288|| MMU_INST_PADDR_EXT  ||   25   || Physical address extension for inst access  || W    ||
    285289
    286290'''Note''': A change to this table should be synchronised with https://www.soclib.fr/trac/dev/wiki/Component/Iss2Api
     
    359363double words LL & SC accesses (section 4.13 & section 4.14).
    360364
    361 === 4.13 MMU_DOUBLE_LL ===
    362 
    363 The value written in the '''MMU_DOUBLE_LL''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Linked Load transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The read value is written in the MMU_WORD_HI & MMU_WORD_LO registers. This is a blocking request for the processor.
    364 
    365 === 4.14 MMU_DOUBLE_SC ===
    366 
    367 The value written in the'''MMU_DOUBLE_SC''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Store Conditionnal transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The transmitted data are the values stored in the he MMU_WORD_HI & MMU_WORD_LO registers. The returned value is written in the MMU_WORD_LO register. This is a blocking request for the processor.
    368 
    369 === 4.15 MMU_ICACHE_PA_INV & MMU_DCACHE_PA_INV ===
     365
     366=== 4.13 MMU_ICACHE_PA_INV & MMU_DCACHE_PA_INV ===
    370367
    371368Writing any value in the '''MMU_ICACHE_PA_INV''' register (resp. '''MMU_DCACHE_PA_INV''' register) can invalidate a cache line in the instruction cache (resp. data cache).
     
    373370If the instruction cache (resp. data cache) contains a cache line corresponding to this address, it is invalidated.
    374371This is a blocking request for the processor.
     372
     373=== 4.14 MMU_DOUBLE_LL ===
     374
     375The value written in the '''MMU_DOUBLE_LL''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Linked Load transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The read value is written in the MMU_WORD_HI & MMU_WORD_LO registers. This is a blocking request for the processor.
     376
     377=== 4.15 MMU_DOUBLE_SC ===
     378
     379The value written in the'''MMU_DOUBLE_SC''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Store Conditionnal transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The transmitted data are the values stored in the he MMU_WORD_HI & MMU_WORD_LO registers. The returned value is written in the MMU_WORD_LO register. This is a blocking request for the processor.
     380
     381=== 4.16 MMU_DATA_PADDR_EXT ===
     382
     383The value written in the '''MMU_DATA_PADDR_EXT''' register is used as a physical address extension during a data access. It is only used when the DTLB is deactivated. It is used to access a memory location which is beyond the 4 Gbytes address space.
     384
     385=== 4.17 MMU_INST_PADDR_EXT ===
     386
     387The value written in the '''MMU_INST_PADDR_EXT''' register is used as a physical address extension during an instruction access. It is only used when the ITLB is deactivated. It is used to access a memory location which is beyond the 4 Gbytes address space.
     388