Changes between Version 5 and Version 6 of VirtualMemory


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Timestamp:
Jun 27, 2009, 7:27:59 PM (13 years ago)
Author:
alain
Comment:

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  • VirtualMemory

    v5 v6  
    33= TSAR virtual memory =
    44
    5 The TSAR MMU can be used with any 32 bits, single instruction issue, processor.
    6 In order to be independent on the processor core choice, the TLB MISS are handled by an hardwired Finite State Machine (called a Table Walk), without software action. 
     5The TSAR MMU (Memory Management Unit) is an hardware component implemented in the L1 cache controller. This cache controller is a generic component that can be used with any 32 bits, single instruction issue, processor. As any MMU, the generic TSAR MMU is in charge of the virtual to physical address translation, and perfom various
     6access right verification. It implements a paginated virtual memory, supporting two page sizes : 4 Kbytes pages, and 2 Mbytes pages.
     7
     8As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches,
     9sharing the same physical access to the VCI/OCP interconnect. These L1 caches use physical addresses.
     10Similarly, the L1 cache controller contains two separated hardware MMUs for instruction and data. 
     11In order to be independent on the processor core choice, the TLB MISS are handled by an hardwired Finite State Machine (called a Table Walk), without any software action. 
    712
    813== 1. Page Table Organisation ==
     
    99104== 2. Generic MMU ==
    100105
    101 For each TSAR programmable processor, the generic MMU is implemented as an hardware component in the L1 cache controller. As the processor core can issue two simultaneous instruction and data requests, there is actually two separated hardware MMUs for instruction and data. Each MMU contains a TLB (Translation Look-aside Buffer).
    102 These TLBs are implemented as set-associative caches containing 64 entries (8 sets of 8 ways). Each entry in these TLBs can contain either a 4 Kbytes page descriptor, or a 2 Mbytes page descriptor.
     106For each TSAR programmable processor, the generic MMU is implemented as an hardware component in the L1 cache controller.
     107As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches,
     108sharing the same physical access to the VCI/OCP interconnect. These L1 caches use physical addresses.
     109Similarly, the L1 cache controller contains two separated hardware MMUs for instruction and data. Each MMU contains a 64 entries TLB (Translation Look-aside Buffer).
     110These TLBs are implemented as set-associative caches (8 sets of 8 ways). Each entry in these TLBs can contain either a 4 Kbytes page descriptor, or a 2 Mbytes page descriptor.
    103111
    104112For both data & instructions, the TSAR L1 caches use physical addresses (the tags contained in the directories are obtained from the physical addresses).
    105113The access to the L1 cache being a critical path, the TSAR MMU use a speculative approach to avoid to serialize the TLB access and the L1 cache access.
    106114
    107 === 2.1 Generic MMU activation
     115=== 2.1 Generic MMU activation ===
    108116
    109117After general RESET the generic MMU is desactivated : As long as the MMU is not activated, the 32 bits virtual address is simply extended to 40 bits,
     
    112120=== 2.2 Generic MMU exceptions ===
    113121
    114 === 2.1 generic MMU registers mapping ===
     122=== 2.3 generic MMU registers mapping ===
    115123
    116 The following registers are the  by appending
     124The software controlled following registers are the  by appending
    117125
    118126