Changes between Version 6 and Version 7 of VirtualMemory


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Timestamp:
Jun 28, 2009, 12:56:46 AM (13 years ago)
Author:
alain
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  • VirtualMemory

    v6 v7  
    33= TSAR virtual memory =
    44
    5 The TSAR MMU (Memory Management Unit) is an hardware component implemented in the L1 cache controller. This cache controller is a generic component that can be used with any 32 bits, single instruction issue, processor. As any MMU, the generic TSAR MMU is in charge of the virtual to physical address translation, and perfom various
    6 access right verification. It implements a paginated virtual memory, supporting two page sizes : 4 Kbytes pages, and 2 Mbytes pages.
     5The TSAR MMU (Memory Management Unit) is an hardware component implemented in the L1 cache controller. This cache controller is a generic component that can be used with any  single instruction issue, 32 bits processor. As any MMU, the generic TSAR MMU is in charge of the virtual to physical address translation, and perfoms
     6access right verifications. It implements a paginated virtual memory, supporting two page sizes : 4 Kbytes pages, and 2 Mbytes pages.
    77
    88As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches,
     
    1313== 1. Page Table Organisation ==
    1414
    15 The TSAR virtual memory uses a paged approach. The TSAR architecture defines two page sizes :
     15The TSAR virtual memory uses a paginated approach. The TSAR architecture defines two page sizes :
    1616-       4 Kbytes pages
    1717-       2 Mbytes pages
     
    3030-       All page tables (first & second level) must be aligned : the page table base adress must be a multiple of 8K bytes for a first level page table, and multiple of 4K bytes for a second level page table.
    3131-       The page tables can be placed anywhere in the physical address space.
    32 -       The PTPR register (located in the generic MMU, and initialised by  the OS at each context switch) contains actually the 26 MSB bits  of the first level page table base address. It must be extended (left-shifted) to 36 bits by the hardware.
     32-       The PTPR register (located in the generic MMU, and initialised by  the OS at each context switch) contains actually the 27 MSB bits  of the first level page table base address. In case of TLB MISS, it is extended (left-shifted) to 40 bits by the hardware.
    3333
    3434=== 1.2 First Level Page Table Entry Format ===