Changes between Version 7 and Version 8 of VirtualMemory


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Timestamp:
Jun 28, 2009, 10:43:21 AM (13 years ago)
Author:
alain
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  • VirtualMemory

    v7 v8  
    1313== 1. Page Table Organisation ==
    1414
    15 The TSAR virtual memory uses a paginated approach. The TSAR architecture defines two page sizes :
    16 -       4 Kbytes pages
    17 -       2 Mbytes pages
     15The TSAR architecture defines two page sizes : 4 Kbytes pages, and 2 Mbytes pages.
    1816The virtual address space size is 4 Gbytes (32 bits virtual addresses).
    1917The physical address space is limited to 1 Tbytes (40 bits physical addresses).
    20 
    21 The page table are build by the operating system, and are stored in memory. They are used for both the VPN (Virtual Page number)  to PPN (Physical Page Number) translation, and for access rights checking.
     18The page table are build by the operating system, and are stored in the main memory.
    2219
    2320=== 1.1 Two levels Page Table structure ===
     
    2522As described below, the Page Table has a hierarchical two levels structure :
    2623
     24[[Image(two.png, nolink)]]
    2725
    28 
    29 The general mapping constraints are the following
    30 -       All page tables (first & second level) must be aligned : the page table base adress must be a multiple of 8K bytes for a first level page table, and multiple of 4K bytes for a second level page table.
    31 -       The page tables can be placed anywhere in the physical address space.
    32 -       The PTPR register (located in the generic MMU, and initialised by  the OS at each context switch) contains actually the 27 MSB bits  of the first level page table base address. In case of TLB MISS, it is extended (left-shifted) to 40 bits by the hardware.
     26 * All page tables (first & second level) must be aligned : the page table base adress must be a multiple of 8K bytes for a first level page table, and multiple of 4K bytes for a second level page table.
     27 * The page tables can be placed anywhere in the physical address space.
     28 * The PTPR register is located in the generic MMU, and is re-initialised by  the OS at each context switch. It contains the 27 MSB bits  of the first level page table base address, and is extended (left-shifted) to 40 bits by the Table-Walk FSM in case of TLB MISS.
    3329
    3430=== 1.2 First Level Page Table Entry Format ===