= What is the TSAR project ? =

 * TSAR (Tera-Scale ARchitecture), coherent shared memory, manycore architecture, designed and implemented by the LIP6 laboratory. It supports commodity operating systems such as LINUX or NetBSD. A 96 cores VLSI prototype has been physically implemented by the CEA-LETI in CMOS 28nm,
and the architecture can scale up to 1024 cores.

= TSAR documentation =

 * [wiki:Specification Architecture Overview] 
 * [wiki:VirtualMemory Memory Management Unit]
 * [wiki:CacheCoherence Cache Coherence Protocol]
 * [wiki:AtomicOperations Atomic Operations]
 * [wiki:InterconnexionNetworks Communication Infrastructure]
 * [wiki:Versions Architecture Versions]
 * [wiki:TLMDT TLMDT Modeling]

= TSAR components documentation =

 * [wiki:private/MemoryCacheConfiguration Memory Cache Configuration Interface]
 * [wiki:private/MemoryCacheFSMs Memory Cache FSMs]

= Testing TSAR virtual prototype =

 * Install [https://www.soclib.fr/ SoCLib]
 * Checkout Tsar modules
{{{
$ svn co https://www-soc.lip6.fr/svn/tsar/trunk tsar
}}}
 * Add the newly created `tsar` directory to `soclib-cc`; add the following line in your `~/.soclib/global.conf`:
{{{
config.addDescPath("/path/to/tsar")
}}}
 * Go to `tsar/platforms` and try the prototypes
 * subscribe to the [[https://www-soc.lip6.fr/wws/info/tsar-commit|tsar-commit]]
   mailing list to receive notifications on TSAR svn commits

= Keywords =

 * Multi-core and Many-core Architecture
 * Cache Coherence Protocol
 * Shared Memory
 * CC-NUMA