Lionel Lacassagne
Laboratoire d'Informatique de Paris 6 (LIP6) - Sorbonne University (formely UPMC)
ALSOC team
Publications
International Journals
  1. IEEE Transactions on Parallel and Distributed Systems (TPDS) 2022: "Max-tree Computation on GPUs" E. Carlinet, N. Blin, F. Lemaitre, L. Lacassagne, T. Geraud, 2022 (IEEE link).
  2. JRTIP Journal of Real Time Image Processing: "Parallel Light Speed Labeling: an efficient connected component algorithm for labeling and analysis on multi-core processors" L. Cabaret, L. Lacassagne, D. Etiemble, 2018 (Springer Link).
  3. JRTIP Journal of Real Time Image Processing "Light Speed Labeling: Efficient Connected Component Labeling on RISC Architectures" L. Lacassagne, B. Zavidovique , pp. 117-135, 2010 (Springer Link).
International Conferences and Workshops
  1. BNBW 2022 "LSL3D: a run-based Connected Component Labeling algorithm for 3D volumes", N. Maurice,F. Lemaitre, J. Sopena, L. Lacassagne, Binary is the new Black (and White) workshop @ ICIAP 2022 (slides)
  2. BNBW 2022 "An efficient run-based Connected Component Labeling algorithm for processing holes", F. Lemaitre, N. Maurice, L. Lacassagne, Binary is the new Black (and White) workshop @ ICIAP 2022 (slides)

  3. ICASSP 2021 "Taming Voting Algorithms on GPUs for an Efficient Connected Component Analysis Algorithm", F. Lemaitre, A. Hennequin, L. Lacassagne, IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) 2021 IEEE link(slides)
  4. GTC 2021 "Taming Voting Algorithms on GPUs for an Efficient Connected Component Analysis Algorithm", F. Lemaitre, A. Hennequin, L. Lacassagne, GPU Technology Conference (GTC) 2021
  5. PPoPP/WPMVP 2020 "How to speed Connected Component Labeling up with SIMD RLE algorithms", F. Lemaitr, A. Hennequin, L. Lacassagne, Workshop on programming models for SIMD/Vector processing (WPMVP), ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP) 2020
  6. PPoPP/WPMVP 2019 "Designing efficient SIMD algorithms for direct CCL", A. Hennequin, I. Masliah, L. Lacassagne, Workshop on programming models for SIMD/Vector processing (WPMVP), ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP) 2019
  7. GTC 2019 San Jose "A New Direct Connected Component Labeling and Analysis Algorithm for GPUs", A. Hennequin, L. Lacassagne, GPU Technology Conference (GTC) @ San Jose 2019 video @ Nvidia + slides @ Nvidia
  8. DASIP 2019 SparseCCL "SparseCCL: Connected Components Labeling and Analysis for sparse images", A. Hennequin, B. Couturier, V. Gligorov, L. Lacassagne, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2019
  9. DASIP 2018 "A new Direct Connected Component Labeling and Analysis Algorithms for GPUs", A. Hennequin, L. Lacassagne, L. Cabaret, Q. L. Meunier, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2018

  10. GTC 2017 "Distanceless Label Propagation: an Efficient Direct Connected Component Labeling Algorithm for GPUs", L. Cabaret, L. Lacassagne, D. Etiemble, International GPU Technical Conference, Munchen, (poster).
  11. PPoPP/WPMVP 2016 "A new SIMD iterative connected component labeling algorithm", L. Lacassagne, L. Cabaret, D. Etiemble, F. Hebache, A. Petreto, ACM International Workshop on Programming Models for SIMD/Vector (WPMVP) @ Principles and Practice of Parallel Programming Conference (PPoPP), 2016
  12. ICIP 2015 "Parallel Light Speed Labeling: an efficient connected component labeling algorithm for multi-core processors", L. Cabaret, L. Lacassagne, D. Etiemble, IEEE International Conference on Image Processing, 2015
  13. SiPS 2014 "What Is the World’s Fastest Connected Component Labeling Algorithm?", L. Cabaret, L. Lacassagne, IEEE International Workshop on Signal Processing Systems, 2014
  14. DASIP 2014 "A Review of World’s Fastest Connected Component Labeling Algorithms: Speed and Energy Estimation", L. Cabaret, L. Lacassagne, L. Oudni, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2014.
  15. ICSIPA 2009 "Video rate image segmentation by means of region splitting and merging", K. Aneja, F. Laguzet, L. Lacassagne, A. Mérigot, IEEE International Conference on Signal and Image Processing Applications
  16. ICIP 2009 "Light Speed Labeling for RISC architectures", L. Lacassagne, B. Zavidovique. IEEE International Conference on Image Processing, 2009, pp. 3245-3248.

  17. CAMP 2005 "Implementating Motion Markov Detection on General Purpose Processor and Associative Mesh", J. Denoulet, G.Mostafaoui, L.Lacassagne, A. Mérigot, IEEE Computer Architecture and Machine Perception, 2005, pp. 288-283.
  18. ICTTA 2004, "A Fast image segmentation scheme", T. Kunlin, L. Lacassagne, A. Mérigot, International Conference on Information & Communication Technologies : from Theory to Applications, 2004, pp. 351-352.
  19. ICIAP 1999 "Motion detection, labeling, data association and tracking in real time on RISC computer", L. Lacassagne, M. Milgram, P. Garda, Septembre à Venise, Italy (this pdf is correct, no that on IEEE site), International Conference on Image Analysis and Processing, 1999, pp. 520-525.
National Conferences and Workshops
  1. Compas 2021 "Un nouvel algorithme efficace de Split & Merge pour systèmes embarqués", N. Maurice, J. Sopena, L. Lacassagne, Compas 2021 (slides)
  2. Compas 2019 "Étiquetage et analyse en composantes connexes sur GPU", A. Hennequin, L. Lacassagne, I. Masliah, Compas 2019 (slides)
  3. GRETSI 2003 "Extraction de trajectoires basées sur la cinématique dans les séquences d'images", G. Mostafaoui, C. Achard, M. Milgram, L. Lacassagne, GRETSI 2003, France
  4. AAA 2000 (soon recompilation) "Light Speed Labelling: un nouvel algorithme d'étiquetage en composantes connexes", L. Lacassagne, M. Milgram, J. Devars, Congrès Adéquation Algorithme Architecture, 2000, France
  5. GRETSI 1999 "Implémentation temps réel d'algorithme de détection de mouvement par champs de Markov sur RISC et DSP C6x", L. Lacassagne, F. Lohier, M. Milgram, P. Garda; GRETSI 1999, France