Example :
from stratus import *
class inst_rom4 ( Model ) :
def Interface ( self ) :
self.sel0 = SignalIn ( "sel0", 1 )
self.sel1 = SignalIn ( "sel1", 1 )
self.q = SignalOut ( "dataout", 4 )
self.vdd = VddIn ( "vdd" )
self.vss = VssIn ( "vss" )
def Netlist ( self ) :
Generate ( 'DpgenRom4', 'rom4_0b1010_0b1100_0b1111_0b0001'
, param = { 'nbit' : 4
, 'val0' : "0b1010"
, 'val1' : "0b1100"
, 'val2' : "0b1111"
, 'val3' : "0b0001"
, 'physical' : True
}
)
self.I = Inst ( 'rom4_0b1010_0b1100_0b1111_0b0001', 'inst'
, map = { 'sel0' : self.sel0
, 'sel1' : self.sel1
, 'q' : self.q
, 'vdd' : self.vdd
, 'vss' : self.vss
}
)
def Layout ( self ) :
Place ( self.I, NOSYM, Ref(0, 0) )