Example :
from stratus import *
class inst_ram ( Model ) :
def Interface ( self ) :
self.ck = SignalIn ( "ck", 1 )
self.w = SignalIn ( "w", 1 )
self.selram = SignalIn ( "selram", 1 )
self.ad = SignalIn ( "ad", 5 )
self.datain = SignalIn ( "datain", 32 )
self.dataout = TriState ( "dataout", 32 )
self.vdd = VddIn ( "vdd" )
self.vss = VssIn ( "vss" )
def Netlist ( self ) :
Generate ( 'DpgenRam', 'ram_32_32'
, param = { 'nbit' : 32
, 'nword' : 32
, 'physical' : True
}
)
self.I = Inst ( 'ram_32_32', 'inst'
, map = { 'ck' : self.ck
, 'w' : self.w
, 'selram' : self.selram
, 'ad' : self.ad
, 'datain' : self.datain
, 'dataout' : self.dataout
, 'vdd' : self.vdd
, 'vss' : self.vss
}
)
def Layout ( self ) :
Place ( self.I, NOSYM, Ref(0, 0) )