source: trunk/hal/tsar_mips32/drivers/soclib_pic.c @ 359

Last change on this file since 359 was 337, checked in by alain, 7 years ago

Introduce the delayed context switch if current thread has a lock.

File size: 18.7 KB
RevLine 
[75]1/*
2 * soclib_pic.c - soclib PIC driver implementation.
3 *
[188]4 * Author  Alain Greiner (2016,2017)
[141]5 *
[75]6 * Copyright (c) UPMC Sorbonne Universites
7 *
8 * This file is part of ALMOS-MKH.
9 *
[141]10 * ALMOS-MKH is free software; you can redistribute it and/or modify it
[75]11 * under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2.0 of the License.
13 *
[141]14 * ALMOS-MKH is distributed in the hope that it will be useful, but
[75]15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
[141]20 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
[75]21 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#include <hal_types.h>
25#include <chdev.h>
26#include <soclib_pic.h>
27#include <errno.h>
28#include <string.h>
29#include <vfs.h>
[296]30#include <rpc.h>
[188]31#include <cluster.h>
32#include <printk.h>
33#include <core.h>
34#include <thread.h>
[75]35
[188]36//////////////////////////////////////////////////////////////////////////////////////
37//         Extern variables
38//////////////////////////////////////////////////////////////////////////////////////
39
40extern  chdev_directory_t chdev_dir;    // defined in chdev.h / allocated in kerneL-init.c
41
42extern  iopic_input_t  iopic_input;  // defined in dev_pic.h / allocated in kernel_init.c
43extern  lapic_input_t  lapic_input;  // defined in dev_pic.h / allocated in kernel_init.c
44 
45//////////////////////////////////////////////////////////////////////////////////////
46//        SOCLIB PIC private functions
47//////////////////////////////////////////////////////////////////////////////////////
48
49///////////////////////////////
50uint32_t soclib_pic_wti_alloc()
51{
52    uint32_t index;
53
54    // get pointer on cluster extension for SOCLIB PIC (XCU descriptor)
55    soclib_pic_cluster_t * ext_ptr = LOCAL_CLUSTER->pic_extend;
56
57    assert( (ext_ptr->first_free_wti < ext_ptr->wti_nr) , __FUNCTION__ ,
58            "no free WTI found : too much external IRQs\n");
59
60    // update WTI allocator
61    index = ext_ptr->first_free_wti;
62    ext_ptr->first_free_wti++;
63
64    return index;
65
66}  // end soclib_pic_wti_alloc()
67
68///////////////////////////////////////
69inline uint32_t * soclib_pic_xcu_base()
70{
[205]71    return ((soclib_pic_cluster_t *)(LOCAL_CLUSTER->pic_extend))->xcu_base;
72}
[188]73
[205]74/////////////////////////////////////////////////////////
75inline uint32_t * soclib_pic_remote_xcu_base( cxy_t cxy )
76{
77    soclib_pic_cluster_t * extend;
[188]78
[205]79    // get extended pointer on PIC extension in remote cluster
80    extend = hal_remote_lpt( XPTR( cxy , &cluster_manager.pic_extend ) );
[188]81
[205]82        return (uint32_t *)hal_remote_lpt( XPTR( cxy , &extend->xcu_base ) );
83                 
84}
85
[188]86///////////////////////////////////////////
87void soclib_pic_xcu_status( lid_t      lid,
88                            uint32_t * hwi_status,
89                            uint32_t * wti_status,
90                            uint32_t * pti_status )
91{
92    // get local XCU segment base
93        uint32_t * base = soclib_pic_xcu_base();
94
95    // read PRIO register
96        uint32_t prio = base[(XCU_PRIO << 5) | lid];
97
98    *wti_status = (prio & 0x4) ? (((prio >> 24) & 0x1F) + 1) : 0;
99    *hwi_status = (prio & 0x2) ? (((prio >> 16) & 0x1F) + 1) : 0;
100    *pti_status = (prio & 0x1) ? (((prio >>  8) & 0x1F) + 1) : 0;
101
102}
103
[279]104////////////////////////////////////////////////////
105inline uint32_t soclib_pic_xcu_ack( uint32_t * reg )
106{
107    return *reg;
108}
109
[188]110/////////////////////////////
111void soclib_pic_irq_handler()
112{
113    uint32_t   hwi_status;   // HWI index + 1  / no pending HWI if 0
114    uint32_t   wti_status;   // WTI index + 1  / no pending WTI if 0
115    uint32_t   pti_status;   // PTI index + 1  / no pending PTI if 0
116    chdev_t  * src_chdev;    // pointer on source chdev descriptor
[279]117    uint32_t   index;        // WTI / HWI / PTI index
118    uint32_t   ack;          // XCU acknowledge requires a read...
[188]119
120    core_t * core = CURRENT_THREAD->core;
121
122    // get XCU status
123    soclib_pic_xcu_status( core->lid,
124                           &hwi_status,
125                           &wti_status,
126                           &pti_status );
127
[296]128    irq_dmsg("\n[INFO] %s : enter for core[%x,%d] / WTI = %x / HWI = %x / WTI = %x\n",
129             __FUNCTION__ , local_cxy , core->lid , wti_status , hwi_status , pti_status );
[279]130
[188]131    // analyse status and handle up to 3 pending IRQ (one WTI, one HWI, one PTI)
132
133    if( wti_status )          // pending WTI
134        {
135        index = wti_status - 1;
136
137        if( index < LOCAL_CLUSTER->cores_nr )   // it is an IPI
138        {
139            assert( (index == core->lid) , __FUNCTION__ , "illegal IPI index" );
140
[337]141            // read mailbox content to acknowledge WTI,
[279]142            uint32_t * base = soclib_pic_xcu_base();
143            ack = base[(XCU_WTI_REG << 5) | core->lid];
[337]144           
[296]145            // check RPC FIFO,  and activate or create a RPC thread
[337]146            // condition is always true, but we must use the ack value
147            if( ack + 1 ) rpc_check();
[188]148        }
149        else                                    // it is an external device
150        {
151            // get pointer on source chdev
152            src_chdev = ((soclib_pic_core_t *)core->pic_extend)->wti_vector[index];
153
154                    if( src_chdev == NULL )        // strange, but not fatal
155                    {
156                printk("\n[WARNING] in %s : no handler for WTI %d on core %d in cluster %x\n",
157                       __FUNCTION__ , index , core->lid , local_cxy );
158
159                    core->spurious_irqs ++;
160
[279]161                // disable WTI in local XCU controller
162                uint32_t * base = soclib_pic_xcu_base();
163                base[(XCU_MSK_WTI_DISABLE << 5) | core->lid] = 1 << core->lid;
[188]164            }
165            else                                 // call relevant ISR
166            {
167                        irq_dmsg("\n[INFO] %s received WTI : index = %d for core %d in cluster %d\n",
168                         __FUNCTION__ , index , core->lid , local_cxy );
169
170                // call ISR
171                    src_chdev->isr( src_chdev );
172            }
173        }
174        }
175
176        if( hwi_status )      // pending HWI
177        {
178        index = hwi_status - 1;
179
180        // get pointer on source chdev
181        src_chdev = ((soclib_pic_core_t *)core->pic_extend)->hwi_vector[index];
182
183                if( src_chdev == NULL )        // strange, but not fatal
184                {
185            printk("\n[WARNING] in %s : no handler for HWI %d on core %d in cluster %x\n",
186                   __FUNCTION__ , index , core->lid , local_cxy );
187
188                core->spurious_irqs ++;
189
[279]190            // disable HWI in local XCU controller
191            uint32_t * base = soclib_pic_xcu_base();
192            base[(XCU_MSK_HWI_DISABLE << 5) | core->lid] = 1 << core->lid;
[188]193                }
194        else                    // call relevant ISR
195        {
196                    irq_dmsg("\n[INFO] %s received HWI : index = %d for core %d in cluster %d\n",
197                     __FUNCTION__ , index , core->lid , local_cxy );
198
199            // call ISR
200                    src_chdev->isr( src_chdev );
201        }
202        }
203
204    if( pti_status )      // pending PTI
205        {
206        index = pti_status - 1;
207
208                irq_dmsg("\n[INFO] %s received PTI : index = %d for cpu %d in cluster %d\n",
209                 __FUNCTION__ , index , core->lid , local_cxy );
210
211        assert( (index == core->lid) , __FUNCTION__ , "unconsistent PTI index\n");
212
213        // acknowledge PTI
[279]214        uint32_t * base = soclib_pic_xcu_base();
215        ack = base[(XCU_PTI_ACK << 5) | core->lid];
[188]216
[279]217        // execute all actions related to TICK event
[188]218        core_clock( core );
219        }
220}  // end soclib_pic_irq_handler()
221
222
223
224
225//////////////////////////////////////////////////////////////////////////////////////
226//         SOCLIC PIC device  generic API
227//////////////////////////////////////////////////////////////////////////////////////
228
229/////////////////////////////////////
230void soclib_pic_init( chdev_t * pic )
231{
232    uint32_t    i;      // for loop on IOPIC inputs
233    uint32_t    x;      // for loop on clusters in a row
234    uint32_t    y;      // for loop on clusters in a column inputs
235    uint32_t    lid;    // for loop on cores in a cluster
236
237    // get target architecture parameters
238    cluster_t * cluster = LOCAL_CLUSTER;
239    uint32_t    x_size  = cluster->x_size;
240    uint32_t    y_size  = cluster->y_size;
241    uint32_t    y_width = cluster->y_width;
242    uint32_t    ncores  = cluster->cores_nr;
243
244    // get IOPIC controller cluster and segment base pointer
245    cxy_t      iopic_seg_cxy = (cxy_t)GET_CXY( pic->base );
246    uint32_t * iopic_seg_ptr = (uint32_t *)GET_PTR( pic->base );
247
248    // reset the IOPIC component registers : mask all input IRQs
249    for( i = 0 ; i < CONFIG_MAX_EXTERNAL_IRQS ; i++ )
250    {
251        xptr_t iopic_seg_xp = XPTR( iopic_seg_cxy,
252                                    iopic_seg_ptr + i*IOPIC_SPAN + IOPIC_MASK ); 
253        hal_remote_sw( iopic_seg_xp , 0 ); 
254    }
255   
256    // GET XCU controller segment base
257    uint32_t * base = soclib_pic_xcu_base();
258
259    // reset the XCU component registers in all clusters:
260    // mask all HWIs, all WTIs, and all PTIs, for all cores   
261    for( x = 0 ; x < x_size ; x++ )
262    {
263        for( y = 0 ; y < y_size ; y++ )
264        {
265            for( lid = 0 ; lid < ncores ; lid++ )
266            {
267                cxy_t cxy = (x<<y_width) + y;
268                xptr_t hwi_mask_xp = XPTR( cxy , base + (XCU_MSK_HWI_DISABLE << 5 | lid) );
269                xptr_t wti_mask_xp = XPTR( cxy , base + (XCU_MSK_WTI_DISABLE << 5 | lid) );
270                xptr_t pti_mask_xp = XPTR( cxy , base + (XCU_MSK_PTI_DISABLE << 5 | lid) );
271                hal_remote_sw( hwi_mask_xp , 0xFFFFFFFF );
272                hal_remote_sw( wti_mask_xp , 0xFFFFFFFF );
273                hal_remote_sw( pti_mask_xp , 0xFFFFFFFF );
274            }
275        }
276    }
277}  // end soclib_pic_init()
278
279//////////////////////////////////////////////////
280void soclib_pic_extend_init( uint32_t * xcu_base )
281{
282    soclib_pic_cluster_t * cluster_ext_ptr;   
283    soclib_pic_core_t    * core_ext_ptr;
284    kmem_req_t             req;
285    uint32_t               lid;
286    uint32_t               idx;
287
288    cluster_t            * cluster = LOCAL_CLUSTER;
289
290    // create core extension for all cores in cluster
291    for( lid = 0 ; lid < cluster->cores_nr ; lid++ )
292    {
293        // allocate memory for core extension
294        req.type     = KMEM_GENERIC;
295        req.size     = sizeof(soclib_pic_core_t);
296        req.flags    = AF_KERNEL;
297        core_ext_ptr = kmem_alloc( &req );
298
299        assert( (core_ext_ptr != NULL) , __FUNCTION__ ,
300                "cannot allocate memory for core extension\n");
301   
302        // reset the HWI / WTI  interrupt vectors
303        for( idx = 0 ; idx < SOCLIB_MAX_HWI ; idx++ ) core_ext_ptr->hwi_vector[idx] = NULL;
304        for( idx = 0 ; idx < SOCLIB_MAX_WTI ; idx++ ) core_ext_ptr->wti_vector[idx] = NULL;
305
306        // register PIC extension in core descriptor
307        cluster->core_tbl[lid].pic_extend = core_ext_ptr;
308    }
309
310    // allocate memory for cluster extension
311    req.type        = KMEM_GENERIC;
312    req.size        = sizeof(soclib_pic_cluster_t);
313    req.flags       = AF_KERNEL;
314    cluster_ext_ptr = kmem_alloc( &req );
315
316    assert( (cluster_ext_ptr != NULL) , __FUNCTION__ ,
317            "cannot allocate memory for cluster extension\n");
318
319    // get XCU characteristics from the XCU config register
320    uint32_t  config = xcu_base[XCU_CONFIG<<5];
321    uint32_t  wti_nr = (config >> 16) & 0xFF; 
322    uint32_t  hwi_nr = (config >> 8 ) & 0xFF; 
323    uint32_t  pti_nr = (config      ) & 0xFF; 
324
325    // initialize the cluster extension
326    // The first WTI slots are for IPIs (one slot per core)
327    cluster_ext_ptr->xcu_base       = xcu_base;
328    cluster_ext_ptr->hwi_nr         = hwi_nr;
329    cluster_ext_ptr->wti_nr         = wti_nr;
330    cluster_ext_ptr->pti_nr         = pti_nr;
331    cluster_ext_ptr->first_free_wti = cluster->cores_nr;
332
333    // register PIC extension in cluster manager
334    cluster->pic_extend = cluster_ext_ptr;
335
336}  // end soclib_pic_extend_init()
337
[75]338////////////////////////////////////////
[188]339void soclib_pic_bind_irq( lid_t     lid,
340                          chdev_t * src_chdev )
[75]341{
[188]342    // get extended & local pointers on PIC chdev descriptor
343    xptr_t     pic_xp  = chdev_dir.pic;
344    cxy_t      pic_cxy = GET_CXY( pic_xp );
345    chdev_t *  pic_ptr = (chdev_t *)GET_PTR( pic_xp );
[75]346
[188]347    // get extended and local pointers on IOPIC  segment base
348    xptr_t     seg_pic_xp  = hal_remote_lwd( XPTR( pic_cxy , &pic_ptr->base ) );
349    cxy_t      seg_pic_cxy = GET_CXY( seg_pic_xp );
350    uint32_t * seg_pic_ptr = (uint32_t *)GET_PTR( seg_pic_xp );
351
352    // get local pointer on XCU segment base
353    uint32_t * seg_xcu_ptr = soclib_pic_xcu_base();
354
355    // get the source chdev functionnal type, channel, and direction
356    uint32_t func    = src_chdev->func;
357    uint32_t channel = src_chdev->channel;
358    bool_t   is_rx   = src_chdev->is_rx;
359
360    if( (func == DEV_FUNC_IOC) || (func == DEV_FUNC_NIC) ||
361        (func == DEV_FUNC_TXT) || (func == DEV_FUNC_IOB) )          // external IRQ => WTI
[75]362    {
[188]363        // get external IRQ index
364        uint32_t  irq_id;   
365        if     (  func == DEV_FUNC_IOC            ) irq_id = iopic_input.ioc[channel];
366        else if(  func == DEV_FUNC_TXT            ) irq_id = iopic_input.txt[channel];
367        else if( (func == DEV_FUNC_NIC) &&  is_rx ) irq_id = iopic_input.nic_rx[channel];
368        else if( (func == DEV_FUNC_NIC) && !is_rx ) irq_id = iopic_input.nic_tx[channel];
369        else if(  func == DEV_FUNC_IOB            ) irq_id = iopic_input.iob;
370        else      assert( false , __FUNCTION__ , "illegal device functionnal type\n");
371
372        // get a WTI mailbox from local XCU descriptor 
373        uint32_t wti_id = soclib_pic_wti_alloc();
374
375        // register IRQ type and index in chdev
376        src_chdev->irq_type = SOCLIB_TYPE_WTI;
377        src_chdev->irq_id   = wti_id;
378
379        // compute extended pointer on WTI mailbox in local XCU
380        xptr_t wti_xp = XPTR( local_cxy , &seg_xcu_ptr[(XCU_WTI_REG << 5) | wti_id] );
381
382            // set the IOPIC_ADDRESS and IOPIC_EXTEND registers in IOPIC
383        uint32_t lsb_wdata = (uint32_t)wti_xp;
384        uint32_t msb_wdata = (uint32_t)(wti_xp >> 32);
385        xptr_t   lsb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+irq_id*IOPIC_SPAN+IOPIC_ADDRESS );
386        xptr_t   msb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+irq_id*IOPIC_SPAN+IOPIC_EXTEND );
387        hal_remote_sw( lsb_xp , lsb_wdata );
388        hal_remote_sw( msb_xp , msb_wdata );
389
390        // unmask IRQ in IOPIC
391        hal_remote_sw( XPTR( seg_pic_cxy , seg_pic_ptr+irq_id*IOPIC_SPAN+IOPIC_MASK ), 1 );
392
393        // update the WTI interrupt vector for core[lid]
394        core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
395        ((soclib_pic_core_t *)core->pic_extend)->wti_vector[wti_id] = src_chdev;
[75]396    }
[188]397    else if( (func == DEV_FUNC_DMA) || (func == DEV_FUNC_MMC) )   // internal IRQ => HWI
398    {
399        // get internal IRQ index
400        uint32_t hwi_id;
401        if( func == DEV_FUNC_DMA ) hwi_id = lapic_input.dma[channel];
402        else                       hwi_id = lapic_input.mmc;
[75]403
[188]404        // register IRQ type and index in chdev
405        src_chdev->irq_type = SOCLIB_TYPE_HWI;
406        src_chdev->irq_id   = hwi_id;
407
408        // update the HWI interrupt vector for core[lid]
409        core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
410        ((soclib_pic_core_t *)core->pic_extend)->wti_vector[hwi_id] = src_chdev;
411    }
412    else
413    {
414        assert( false , __FUNCTION__ , "illegal device functionnal type\n" );
415    } 
416}  // end soclib_pic_bind_irq();
417
[205]418///////////////////////////////////////
419void soclib_pic_enable_irq( lid_t  lid,
420                            xptr_t src_chdev_xp )
[75]421{
[205]422    // get cluster and local pointer on remote src_chdev
423    cxy_t     src_chdev_cxy = GET_CXY( src_chdev_xp );
424    chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp );
[141]425
[205]426    // get local pointer on remote XCU segment base
427    uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy );
428
[188]429    // get the source chdev IRQ type and index
[205]430    uint32_t irq_type = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) );
431    uint32_t irq_id   = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) );
[141]432
[188]433    if( irq_type == SOCLIB_TYPE_HWI )
434    {
[205]435        // enable this HWI in remote XCU controller
436        hal_remote_sw( XPTR( src_chdev_cxy , 
437                       &seg_xcu_ptr[(XCU_MSK_HWI_ENABLE << 5) | lid] ) , (1 << irq_id) );
[188]438    }
439    else if( irq_type == SOCLIB_TYPE_WTI )
440    {
[279]441        // enable this WTI in remote XCU controller
[205]442        hal_remote_sw( XPTR( src_chdev_cxy , 
443                       &seg_xcu_ptr[(XCU_MSK_WTI_ENABLE << 5) | lid] ) , (1 << irq_id) );
[188]444    }
445    else
446    {
447        assert( false , __FUNCTION__ , "illegal IRQ type\n" );
448    }
449} // end soclib_pic_enable_irq()
[75]450
[205]451////////////////////////////////////////
452void soclib_pic_disable_irq( lid_t  lid,
453                             xptr_t src_chdev_xp )
[188]454{
[205]455    // get cluster and local pointer on remote src_chdev
456    cxy_t     src_chdev_cxy = GET_CXY( src_chdev_xp );
457    chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp );
[75]458
[205]459    // get local pointer on remote XCU segment base
460    uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy );
461
[188]462    // get the source chdev IRQ type and index
[205]463    uint32_t irq_type = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) );
464    uint32_t irq_id   = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) );
[75]465
[188]466    if( irq_type == SOCLIB_TYPE_HWI )
467    {
[205]468        // enable this HWI in remote XCU controller
469        hal_remote_sw( XPTR( src_chdev_cxy , 
470                       &seg_xcu_ptr[(XCU_MSK_HWI_DISABLE << 5) | lid] ) , (1 << irq_id) );
[188]471    }
472    else if( irq_type == SOCLIB_TYPE_WTI )
473    {
[279]474        // enable this WTI in remote XCU controller
[205]475        hal_remote_sw( XPTR( src_chdev_cxy , 
476                       &seg_xcu_ptr[(XCU_MSK_WTI_DISABLE << 5) | lid] ) , (1 << irq_id) );
[188]477    }
478    else
479    {
480        assert( false , __FUNCTION__ , "illegal IRQ type\n" );
481    }
482} // end soclib_pic_enable_irq()
[75]483
[188]484///////////////////////////////////////////////
485void soclib_pic_enable_timer( uint32_t period )
[75]486{
[188]487    // calling core local index
488    lid_t  lid = CURRENT_CORE->lid;
[141]489
[188]490    // get XCU segment base
491    uint32_t * base = soclib_pic_xcu_base();
[141]492
[188]493    // set period value in XCU
494    base[(XCU_PTI_PER << 5) | lid] = period;
[75]495
[279]496    // enable PTI in local XCU controller
[188]497    base[(XCU_MSK_PTI_ENABLE << 5) | lid] = 1 << lid;
[75]498}
499
[279]500////////////////////////////
501void soclib_pic_enable_ipi()
502{
503    // calling core local index
504    lid_t  lid = CURRENT_CORE->lid;
505
506    // get XCU segment base
507    uint32_t * base = soclib_pic_xcu_base();
508
509    // enable WTI in local XCU controller
510    base[(XCU_MSK_WTI_ENABLE << 5) | lid] = 1 << lid;
511}
512
[188]513///////////////////////////////////////
514void soclib_pic_send_ipi( cxy_t    cxy,
515                          lid_t    lid )
[75]516{
[188]517    // get pointer on local XCU segment base
518    uint32_t * base = soclib_pic_xcu_base();
[141]519
[188]520    // write to WTI mailbox[cxy][lid]
521    hal_remote_sw( XPTR( cxy , &base[(XCU_WTI_REG << 5) | lid] ) , 0 );
522}
[141]523
[75]524
525
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