Changeset 235 for trunk/hal/x86_64/core/hal_apic.c

Timestamp:

Jul 19, 2017, 10:03:41 AM (7 years ago)

Author:

max@…

Message:

Start adding some code for SMP support

File:

• trunk/hal/x86_64/core/hal_apic.c (modified) (6 diffs)

trunk/hal/x86_64/core/hal_apic.c

@@ -58 +58 @@
 #define PIT_FREQUENCY   1193182
 #define HZ              100 /* 1/HZ = 10ms */
+#define muHZ            1000000 /* 1/muHZ = 1 microsecond */
 
 #define PIT_TIMER0      0x40
@@ -79 +80 @@
 #       define CMD_READBACK     0xc0
 
-void hal_pit_init()
-{
-        /* Initialize PIT clock 0 to the maximum counter value, 65535. */
+void hal_pit_reset(uint16_t val)
+{
+        pit_ticks_base = 0;
+
+        /* Initialize PIT clock 0 to value given. */
         out8(PIT_CMD, CMD_COUNTER0|CMD_MODE2|CMD_16BIT);
-        out8(PIT_TIMER0, 0xFF);
-        out8(PIT_TIMER0, 0xFF);
+        out8(PIT_TIMER0, (val >> 0) & 0xFF);
+        out8(PIT_TIMER0, (val >> 8) & 0xFF);
 }
 
@@ -110 +113 @@
 
         return ticks;
+}
+
+/*
+ * Wait approximately n microseconds.
+ */
+void
+hal_pit_delay(uint64_t n)
+{
+        uint64_t nticks;
+
+        nticks = 0;
+        hal_pit_reset(0);
+
+        while (n > 0) {
+                while (hal_pit_timer_read() - nticks < (PIT_FREQUENCY + muHZ/2) / muHZ) {
+                        /* Wait 1/muHZ sec = 1 microsecond */
+                }
+                nticks++;
+                n--;
+        }
 }
 
@@ -345 +368 @@
 }
 
+static void hal_lapic_icr_wait()
+{
+        while ((hal_lapic_read(LAPIC_ICRLO) & LAPIC_DLSTAT_BUSY) != 0) {
+                pause();
+        }
+}
+
 /*
  * Use the PIT, which has a standard clock frequency, to determine the CPU's
@@ -357 +387 @@
         hal_lapic_write(LAPIC_ICR_TIMER, 0xFFFFFFFF);
 
-        /* Initialize the PIT */
-        hal_pit_init();
+        /* Reset the PIT */
+        hal_pit_reset(-1);
 
         pittick = hal_pit_timer_read() + 1;
@@ -423 +453 @@
 /* -------------------------------------------------------------------------- */
 
+static void
+hal_ipi_init(uint32_t gid)
+{
+        /* clear the error status */
+        hal_lapic_write(LAPIC_ESR, 0);
+        (void)hal_lapic_read(LAPIC_ESR);
+
+        /* send the IPI */
+        hal_lapic_write(LAPIC_ICRHI, gid << LAPIC_ID_SHIFT);
+        hal_lapic_write(LAPIC_ICRLO, LAPIC_DLMODE_INIT | LAPIC_LEVEL_ASSERT);
+        hal_lapic_icr_wait();
+
+        /* wait 10ms */
+        hal_pit_delay(10000);
+
+        hal_lapic_write(LAPIC_ICRLO,
+            LAPIC_DLMODE_INIT | LAPIC_TRIGGER_LEVEL | LAPIC_LEVEL_DEASSERT);
+        hal_lapic_icr_wait();
+}
+
+static void
+hal_ipi_startup(uint32_t gid, paddr_t pa)
+{
+        /* clear the error status */
+        hal_lapic_write(LAPIC_ESR, 0);
+        (void)hal_lapic_read(LAPIC_ESR);
+
+        /* send the IPI */
+        hal_lapic_icr_wait();
+        hal_lapic_write(LAPIC_ICRHI, gid << LAPIC_ID_SHIFT);
+        hal_lapic_write(LAPIC_ICRLO, pa | LAPIC_DLMODE_STARTUP |
+            LAPIC_LEVEL_ASSERT);
+        hal_lapic_icr_wait();
+}
+
+/* -------------------------------------------------------------------------- */
+
+int
+start_secondary_cpu(uint32_t gid, paddr_t pa)
+{
+        /*
+         * Bootstrap code must be addressable in real mode and it must be
+         * page-aligned.
+         */
+        XASSERT(pa < 0x10000 && pa % PAGE_SIZE == 0);
+
+        /*
+         * Local cache flush, in case the BIOS has left the AP with its cache
+         * disabled. It may not be able to cope with MP coherency.
+         */
+        wbinvd();
+
+        hal_ipi_init(gid);
+        hal_pit_delay(10000);
+
+        hal_ipi_startup(gid, pa / PAGE_SIZE);
+        hal_pit_delay(200);
+
+        hal_ipi_startup(gid, pa / PAGE_SIZE);
+        hal_pit_delay(200);
+
+        return 0;
+}
+
+/* -------------------------------------------------------------------------- */
+
 void hal_apic_init()
 {