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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp @ 128

Last change on this file since 128 was 128, checked in by rosiere, 15 years ago
1) Correct bug in link two signal 2) Fix error detected with valgrind 3) modif distexe script
Property svn:keywords set to `Id`
File size: 17.2 KB

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1	#ifdef SYSTEMC
2	//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
3	/*
4	* $Id: Reservation_station_transition.cpp 128 2009-06-26 08:43:23Z rosiere $
5	*
6	* [ Description ]
7	*
8	*/
9
10	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h"
11
12	namespace morpheo {
13	namespace behavioural {
14	namespace core {
15	namespace multi_execute_loop {
16	namespace execute_loop {
17	namespace multi_read_unit {
18	namespace read_unit {
19	namespace reservation_station {
20
21	#ifdef SYSTEMC_VHDL_COMPATIBILITY
22	#define dump_queue() \
23	do \
24	{ \
25	log_printf(TRACE,Reservation_station,FUNCTION," * Dump Reservation Station"); \
26	for (uint32_t it_dump=0;it_dump<_param->_size_queue; it_dump++) \
27	if (_queue_valid [it_dump]) \
28	log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \
29	it_dump, \
30	_queue[it_dump]._context_id , \
31	_queue[it_dump]._front_end_id , \
32	_queue[it_dump]._ooo_engine_id , \
33	_queue[it_dump]._rob_id , \
34	_queue[it_dump]._type , \
35	_queue[it_dump]._operation , \
36	_queue[it_dump]._store_queue_ptr_write, \
37	_queue[it_dump]._store_queue_ptr_read , \
38	_queue[it_dump]._store_queue_empty , \
39	_queue[it_dump]._load_queue_ptr_write , \
40	_queue[it_dump]._has_immediat , \
41	_queue[it_dump]._immediat , \
42	_queue[it_dump]._num_reg_ra , \
43	_queue[it_dump]._data_ra_val , \
44	_queue[it_dump]._data_ra , \
45	_queue[it_dump]._num_reg_rb , \
46	_queue[it_dump]._data_rb_val , \
47	_queue[it_dump]._data_rb , \
48	_queue[it_dump]._num_reg_rc , \
49	_queue[it_dump]._data_rc_val , \
50	_queue[it_dump]._data_rc , \
51	_queue[it_dump]._write_rd , \
52	_queue[it_dump]._num_reg_rd , \
53	_queue[it_dump]._write_re , \
54	_queue[it_dump]._num_reg_re , \
55	toString(_queue[it_dump]._type).c_str()); \
56	} while (0)
57	#else
58	#define dump_queue() \
59	do \
60	{ \
61	log_printf(TRACE,Reservation_station,FUNCTION," * Dump Reservation Station"); \
62	log_printf(TRACE,Reservation_station,FUNCTION," * nb_elt : %d",_queue_control->nb_elt()); \
63	for (uint32_t it_dump=0;it_dump<_param->_size_queue; it_dump++) \
64	if (it_dump < _queue_control->nb_elt()) \
65	log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \
66	(*_queue_control)[it_dump], \
67	_queue[(*_queue_control)[it_dump]]._context_id , \
68	_queue[(*_queue_control)[it_dump]]._front_end_id , \
69	_queue[(*_queue_control)[it_dump]]._ooo_engine_id , \
70	_queue[(*_queue_control)[it_dump]]._rob_id , \
71	_queue[(*_queue_control)[it_dump]]._type , \
72	_queue[(*_queue_control)[it_dump]]._operation , \
73	_queue[(*_queue_control)[it_dump]]._store_queue_ptr_write, \
74	_queue[(*_queue_control)[it_dump]]._store_queue_ptr_read , \
75	_queue[(*_queue_control)[it_dump]]._store_queue_empty , \
76	_queue[(*_queue_control)[it_dump]]._load_queue_ptr_write , \
77	_queue[(*_queue_control)[it_dump]]._has_immediat , \
78	_queue[(*_queue_control)[it_dump]]._immediat , \
79	_queue[(*_queue_control)[it_dump]]._num_reg_ra , \
80	_queue[(*_queue_control)[it_dump]]._data_ra_val , \
81	_queue[(*_queue_control)[it_dump]]._data_ra , \
82	_queue[(*_queue_control)[it_dump]]._num_reg_rb , \
83	_queue[(*_queue_control)[it_dump]]._data_rb_val , \
84	_queue[(*_queue_control)[it_dump]]._data_rb , \
85	_queue[(*_queue_control)[it_dump]]._num_reg_rc , \
86	_queue[(*_queue_control)[it_dump]]._data_rc_val , \
87	_queue[(*_queue_control)[it_dump]]._data_rc , \
88	_queue[(*_queue_control)[it_dump]]._write_rd , \
89	_queue[(*_queue_control)[it_dump]]._num_reg_rd , \
90	_queue[(*_queue_control)[it_dump]]._write_re , \
91	_queue[(*_queue_control)[it_dump]]._num_reg_re , \
92	toString(_queue[(*_queue_control)[it_dump]]._type).c_str()); \
93	else \
94	log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d]", \
95	(*_queue_control)[it_dump]); \
96	} while (0)
97	#endif
98
99	#undef FUNCTION
100	#define FUNCTION "Reservation_station::transition"
101	void Reservation_station::transition (void)
102	{
103	log_begin(Reservation_station,FUNCTION);
104	log_function(Reservation_station,FUNCTION,_name.c_str());
105
106	if (PORT_READ(in_NRESET) == 0)
107	{
108	#ifdef SYSTEMC_VHDL_COMPATIBILITY
109	for (uint32_t i=0; i<_param->_size_queue; i++)
110	_queue_valid [i] = false;
111	#else
112	_queue_control->clear();
113	#endif
114
115	for (uint32_t i=0; i<_param->_size_queue; i++)
116	{
117	_queue[i]._context_id = 0; // not necessary
118	_queue[i]._front_end_id = 0; // not necessary
119	_queue[i]._ooo_engine_id = 0; // not necessary
120	_queue[i]._rob_id = 0; // not necessary
121	_queue[i]._operation = 0; // not necessary
122	_queue[i]._type = 0; // not necessary
123	_queue[i]._store_queue_ptr_write = 0; // not necessary
124	_queue[i]._store_queue_ptr_read = 0; // not necessary
125	_queue[i]._store_queue_empty = 0; // not necessary
126	_queue[i]._load_queue_ptr_write = 0; // not necessary
127	_queue[i]._has_immediat = 0; // not necessary
128	_queue[i]._immediat = 0; // not necessary
129	// _queue[i]._read_ra = 0; // not necessary
130	_queue[i]._num_reg_ra = 0; // not necessary
131	_queue[i]._data_ra_val = 0; // not necessary
132	_queue[i]._data_ra = 0; // not necessary
133	// _queue[i]._read_rb = 0; // not necessary
134	_queue[i]._num_reg_rb = 0; // not necessary
135	_queue[i]._data_rb_val = 0; // not necessary
136	_queue[i]._data_rb = 0; // not necessary
137	// _queue[i]._read_rc = 0; // not necessary
138	_queue[i]._num_reg_rc = 0; // not necessary
139	_queue[i]._data_rc_val = 0; // not necessary
140	_queue[i]._data_rc = 0; // not necessary
141	_queue[i]._write_rd = 0; // not necessary
142	_queue[i]._num_reg_rd = 0; // not necessary
143	_queue[i]._write_re = 0; // not necessary
144	_queue[i]._num_reg_re = 0; // not necessary
145	}
146	}
147	else
148	{
149	// ***** POP from reservation station
150
151	// scan in reverse order, because when we pop the queue there are an auto reorder
152	//for (int32_t i=(static_cast<int32_t>(_queue_control->nb_elt()))-1;i>=0; i--)
153	for (int32_t i=(static_cast<int32_t>(_param->_nb_inst_retire))-1;i>=0; i--)
154	{
155	if (( internal_RETIRE_VAL [i] == 1) and
156	(PORT_READ(in_RETIRE_ACK [i]) == 1))
157	{
158	//uint32_t index = (*_queue_control)[i];
159
160	log_printf(NONE,Reservation_station,FUNCTION," * POP [%d]",i);
161
162	uint32_t index = internal_RETIRE_SLOT[i];
163
164	#ifdef SYSTEMC_VHDL_COMPATIBILITY
165	_queue_valid [index] = false;
166	#else
167	_queue_control->pop(index);
168	#endif
169	// cout << "========== Transition : " << endl
170	// << " * i : " << i << endl
171	// << " * index : " << index << endl;
172
173	log_printf(NONE,Reservation_station,FUNCTION," * index : %d",index);
174	}
175	}
176
177	// dump_queue();
178
179	// ***** Bypass
180	// Note : we can take this sequence code before the PUSH in the queue, because read_queue make the bypass !!!
181
182	// scan all entry
183	for (uint32_t i=0;
184	#ifdef SYSTEMC_VHDL_COMPATIBILITY
185	i<_param->_size_queue;
186	#else
187	i<_queue_control->nb_elt();
188	#endif
189	i++)
190	{
191	uint32_t index;
192	#ifdef SYSTEMC_VHDL_COMPATIBILITY
193	index = i;
194	#else
195	index = (*_queue_control)[i];
196	#endif
197
198	// ***** bypass - gpr_write
199	for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
200	{
201	bool cmp;
202	if (_param->_have_port_ooo_engine_id)
203	cmp = (PORT_READ(in_GPR_WRITE_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id);
204	else
205	cmp = true;
206
207	if ((PORT_READ(in_GPR_WRITE_VAL [j]) == 1) and cmp)
208	{
209	if (PORT_READ(in_GPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_ra)
210	{
211	log_printf(TRACE,Reservation_station,FUNCTION," -> GPR_WRITE [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra);
212	_queue[index]._data_ra_val = 1;
213	_queue[index]._data_ra = PORT_READ(in_GPR_WRITE_DATA [j]);
214	}
215	if (PORT_READ(in_GPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_rb)
216	{
217	log_printf(TRACE,Reservation_station,FUNCTION," -> GPR_WRITE [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb);
218	_queue[index]._data_rb_val = 1;
219	_queue[index]._data_rb = PORT_READ(in_GPR_WRITE_DATA [j]);
220	}
221	}
222	}
223	// ***** bypass - spr_write
224	for (uint32_t j=0; j<_param->_nb_spr_write; j++)
225	{
226	bool cmp;
227	if (_param->_have_port_ooo_engine_id)
228	cmp = (PORT_READ(in_SPR_WRITE_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id);
229	else
230	cmp = true;
231
232	if ((PORT_READ(in_SPR_WRITE_VAL [j]) == 1) and
233	cmp and
234	(PORT_READ(in_SPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_rc))
235	{
236	log_printf(TRACE,Reservation_station,FUNCTION," -> SPR_WRITE [%d] - Hit queue[%d]-SPR_RC[%d]",i,index,_queue[index]._num_reg_rc);
237	_queue[index]._data_rc_val = 1;
238	_queue[index]._data_rc = PORT_READ(in_SPR_WRITE_DATA [j]);
239	}
240	}
241	// ***** bypass - bypass_write
242	for (uint32_t j=0; j<_param->_nb_bypass_write; j++)
243	{
244	bool cmp;
245	if (_param->_have_port_ooo_engine_id)
246	cmp = (PORT_READ(in_BYPASS_WRITE_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id);
247	else
248	cmp = true;
249
250	if (cmp)
251	{
252	if (PORT_READ(in_BYPASS_WRITE_GPR_VAL [j]) == 1)
253	{
254	if (PORT_READ(in_BYPASS_WRITE_GPR_NUM_REG[j]) == _queue[index]._num_reg_ra)
255	{
256	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra);
257	_queue[index]._data_ra_val = 1;
258	_queue[index]._data_ra = PORT_READ(in_BYPASS_WRITE_GPR_DATA [j]);
259	}
260	if (PORT_READ(in_BYPASS_WRITE_GPR_NUM_REG [j]) == _queue[index]._num_reg_rb)
261	{
262	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb);
263	_queue[index]._data_rb_val = 1;
264	_queue[index]._data_rb = PORT_READ(in_BYPASS_WRITE_GPR_DATA [j]);
265	}
266	}
267	if ((PORT_READ(in_BYPASS_WRITE_SPR_VAL [j]) == 1) and
268	(PORT_READ(in_BYPASS_WRITE_SPR_NUM_REG[j]) == _queue[index]._num_reg_rc))
269	{
270	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-SPR_RC[%d]",i,index,_queue[index]._num_reg_rc);
271	_queue[index]._data_rc_val = 1;
272	_queue[index]._data_rc = PORT_READ(in_BYPASS_WRITE_SPR_DATA [j]);
273	}
274	}
275	}
276	// ***** bypass - bypass_memory
277	for (uint32_t j=0; j<_param->_nb_bypass_memory; j++)
278	{
279	bool cmp;
280	if (_param->_have_port_ooo_engine_id)
281	cmp = (PORT_READ(in_BYPASS_MEMORY_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id);
282	else
283	cmp = true;
284
285	if ((PORT_READ(in_BYPASS_MEMORY_VAL [j]) == 1) and cmp)
286	{
287	if (PORT_READ(in_BYPASS_MEMORY_NUM_REG [j]) == _queue[index]._num_reg_ra)
288	{
289	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_MEMORY [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra);
290	_queue[index]._data_ra_val = 1;
291	_queue[index]._data_ra = PORT_READ(in_BYPASS_MEMORY_DATA [j]);
292	}
293	if (PORT_READ(in_BYPASS_MEMORY_NUM_REG [j]) == _queue[index]._num_reg_rb)
294	{
295	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_MEMORY [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb);
296	_queue[index]._data_rb_val = 1;
297	_queue[index]._data_rb = PORT_READ(in_BYPASS_MEMORY_DATA [j]);
298	}
299	}
300	}
301	}
302	// ***** PUSH to reservation station
303	if ((PORT_READ(in_INSERT_VAL) == 1) and
304	( internal_INSERT_ACK == 1))
305	{
306	log_printf(TRACE,Reservation_station,FUNCTION," * PUSH");
307
308	// Write in reservation station
309	uint32_t index;
310
311	#ifdef SYSTEMC_VHDL_COMPATIBILITY
312	index = internal_INSERT_SLOT;
313	_queue_valid [internal_INSERT_SLOT] = true;
314	#else
315	index = _queue_control->push();
316	#endif
317	log_printf(TRACE,Reservation_station,FUNCTION," * index : %d",index);
318
319	if (_param->_have_port_context_id)
320	_queue[index]._context_id = PORT_READ(in_INSERT_CONTEXT_ID );
321	if (_param->_have_port_front_end_id)
322	_queue[index]._front_end_id = PORT_READ(in_INSERT_FRONT_END_ID );
323	if (_param->_have_port_ooo_engine_id)
324	_queue[index]._ooo_engine_id = PORT_READ(in_INSERT_OOO_ENGINE_ID );
325	if (_param->_have_port_rob_ptr)
326	_queue[index]._rob_id = PORT_READ(in_INSERT_ROB_ID );
327	_queue[index]._operation = PORT_READ(in_INSERT_OPERATION );
328	_queue[index]._type = PORT_READ(in_INSERT_TYPE );
329	_queue[index]._store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE);
330	_queue[index]._store_queue_ptr_read = PORT_READ(in_INSERT_STORE_QUEUE_PTR_READ );
331	_queue[index]._store_queue_empty = PORT_READ(in_INSERT_STORE_QUEUE_EMPTY );
332	if (_param->_have_port_load_queue_ptr)
333	_queue[index]._load_queue_ptr_write = PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE );
334	_queue[index]._has_immediat = PORT_READ(in_INSERT_HAS_IMMEDIAT );
335	_queue[index]._immediat = PORT_READ(in_INSERT_IMMEDIAT );
336	// _queue[index]._read_ra = PORT_READ(in_INSERT_READ_RA );
337	_queue[index]._num_reg_ra = PORT_READ(in_INSERT_NUM_REG_RA );
338	_queue[index]._data_ra_val = PORT_READ(in_INSERT_DATA_RA_VAL );
339	_queue[index]._data_ra = PORT_READ(in_INSERT_DATA_RA );
340	// _queue[index]._read_rb = PORT_READ(in_INSERT_READ_RB );
341	_queue[index]._num_reg_rb = PORT_READ(in_INSERT_NUM_REG_RB );
342	_queue[index]._data_rb_val = PORT_READ(in_INSERT_DATA_RB_VAL );
343	_queue[index]._data_rb = PORT_READ(in_INSERT_DATA_RB );
344	// _queue[index]._read_rc = PORT_READ(in_INSERT_READ_RC );
345	_queue[index]._num_reg_rc = PORT_READ(in_INSERT_NUM_REG_RC );
346	_queue[index]._data_rc_val = PORT_READ(in_INSERT_DATA_RC_VAL );
347	_queue[index]._data_rc = PORT_READ(in_INSERT_DATA_RC );
348	_queue[index]._write_rd = PORT_READ(in_INSERT_WRITE_RD );
349	_queue[index]._num_reg_rd = PORT_READ(in_INSERT_NUM_REG_RD );
350	_queue[index]._write_re = PORT_READ(in_INSERT_WRITE_RE );
351	_queue[index]._num_reg_re = PORT_READ(in_INSERT_NUM_REG_RE );
352	// dump_queue();
353	}
354	}
355
356	dump_queue();
357
358	end_cycle ();
359
360	log_end(Reservation_station,FUNCTION);
361	};
362
363	}; // end namespace reservation_station
364	}; // end namespace read_unit
365	}; // end namespace multi_read_unit
366	}; // end namespace execute_loop
367	}; // end namespace multi_execute_loop
368	}; // end namespace core
369
370	}; // end namespace behavioural
371	}; // end namespace morpheo
372	#endif
373	//#endif

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