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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp @ 136

Last change on this file since 136 was 136, checked in by rosiere, 15 years ago
1) Add new algo in ifetch queue 2) Add Cancel bit 3) new config
Property svn:keywords set to `Id`
File size: 17.5 KB

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1	#ifdef SYSTEMC
2	//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
3	/*
4	* $Id: Reservation_station_transition.cpp 136 2009-10-20 18:52:15Z rosiere $
5	*
6	* [ Description ]
7	*
8	*/
9
10	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h"
11
12	namespace morpheo {
13	namespace behavioural {
14	namespace core {
15	namespace multi_execute_loop {
16	namespace execute_loop {
17	namespace multi_read_unit {
18	namespace read_unit {
19	namespace reservation_station {
20
21	#ifdef SYSTEMC_VHDL_COMPATIBILITY
22	#define dump_queue() \
23	do \
24	{ \
25	log_printf(TRACE,Reservation_station,FUNCTION," * Dump Reservation Station"); \
26	for (uint32_t it_dump=0;it_dump<_param->_size_queue; it_dump++) \
27	if (_queue_valid [it_dump]) \
28	log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d %.1d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \
29	it_dump, \
30	_queue[it_dump]._context_id , \
31	_queue[it_dump]._front_end_id , \
32	_queue[it_dump]._ooo_engine_id , \
33	_queue[it_dump]._rob_id , \
34	_queue[it_dump]._type , \
35	_queue[it_dump]._operation , \
36	_queue[it_dump]._cancel , \
37	_queue[it_dump]._store_queue_ptr_write, \
38	_queue[it_dump]._store_queue_ptr_read , \
39	_queue[it_dump]._store_queue_empty , \
40	_queue[it_dump]._load_queue_ptr_write , \
41	_queue[it_dump]._has_immediat , \
42	_queue[it_dump]._immediat , \
43	_queue[it_dump]._num_reg_ra , \
44	_queue[it_dump]._data_ra_val , \
45	_queue[it_dump]._data_ra , \
46	_queue[it_dump]._num_reg_rb , \
47	_queue[it_dump]._data_rb_val , \
48	_queue[it_dump]._data_rb , \
49	_queue[it_dump]._num_reg_rc , \
50	_queue[it_dump]._data_rc_val , \
51	_queue[it_dump]._data_rc , \
52	_queue[it_dump]._write_rd , \
53	_queue[it_dump]._num_reg_rd , \
54	_queue[it_dump]._write_re , \
55	_queue[it_dump]._num_reg_re , \
56	toString(_queue[it_dump]._type).c_str()); \
57	} while (0)
58	#else
59	#define dump_queue() \
60	do \
61	{ \
62	log_printf(TRACE,Reservation_station,FUNCTION," * Dump Reservation Station"); \
63	log_printf(TRACE,Reservation_station,FUNCTION," * nb_elt : %d",_queue_control->nb_elt()); \
64	for (uint32_t it_dump=0;it_dump<_param->_size_queue; it_dump++) \
65	if (it_dump < _queue_control->nb_elt()) \
66	log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d %.1d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \
67	(*_queue_control)[it_dump], \
68	_queue[(*_queue_control)[it_dump]]._context_id , \
69	_queue[(*_queue_control)[it_dump]]._front_end_id , \
70	_queue[(*_queue_control)[it_dump]]._ooo_engine_id , \
71	_queue[(*_queue_control)[it_dump]]._rob_id , \
72	_queue[(*_queue_control)[it_dump]]._type , \
73	_queue[(*_queue_control)[it_dump]]._operation , \
74	_queue[(*_queue_control)[it_dump]]._cancel , \
75	_queue[(*_queue_control)[it_dump]]._store_queue_ptr_write, \
76	_queue[(*_queue_control)[it_dump]]._store_queue_ptr_read , \
77	_queue[(*_queue_control)[it_dump]]._store_queue_empty , \
78	_queue[(*_queue_control)[it_dump]]._load_queue_ptr_write , \
79	_queue[(*_queue_control)[it_dump]]._has_immediat , \
80	_queue[(*_queue_control)[it_dump]]._immediat , \
81	_queue[(*_queue_control)[it_dump]]._num_reg_ra , \
82	_queue[(*_queue_control)[it_dump]]._data_ra_val , \
83	_queue[(*_queue_control)[it_dump]]._data_ra , \
84	_queue[(*_queue_control)[it_dump]]._num_reg_rb , \
85	_queue[(*_queue_control)[it_dump]]._data_rb_val , \
86	_queue[(*_queue_control)[it_dump]]._data_rb , \
87	_queue[(*_queue_control)[it_dump]]._num_reg_rc , \
88	_queue[(*_queue_control)[it_dump]]._data_rc_val , \
89	_queue[(*_queue_control)[it_dump]]._data_rc , \
90	_queue[(*_queue_control)[it_dump]]._write_rd , \
91	_queue[(*_queue_control)[it_dump]]._num_reg_rd , \
92	_queue[(*_queue_control)[it_dump]]._write_re , \
93	_queue[(*_queue_control)[it_dump]]._num_reg_re , \
94	toString(_queue[(*_queue_control)[it_dump]]._type).c_str()); \
95	else \
96	log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d]", \
97	(*_queue_control)[it_dump]); \
98	} while (0)
99	#endif
100
101	#undef FUNCTION
102	#define FUNCTION "Reservation_station::transition"
103	void Reservation_station::transition (void)
104	{
105	log_begin(Reservation_station,FUNCTION);
106	log_function(Reservation_station,FUNCTION,_name.c_str());
107
108	if (PORT_READ(in_NRESET) == 0)
109	{
110	#ifdef SYSTEMC_VHDL_COMPATIBILITY
111	for (uint32_t i=0; i<_param->_size_queue; i++)
112	_queue_valid [i] = false;
113	#else
114	_queue_control->clear();
115	#endif
116
117	for (uint32_t i=0; i<_param->_size_queue; i++)
118	{
119	_queue[i]._context_id = 0; // not necessary
120	_queue[i]._front_end_id = 0; // not necessary
121	_queue[i]._ooo_engine_id = 0; // not necessary
122	_queue[i]._rob_id = 0; // not necessary
123	_queue[i]._operation = 0; // not necessary
124	_queue[i]._type = 0; // not necessary
125	_queue[i]._cancel = 0; // not necessary
126	_queue[i]._store_queue_ptr_write = 0; // not necessary
127	_queue[i]._store_queue_ptr_read = 0; // not necessary
128	_queue[i]._store_queue_empty = 0; // not necessary
129	_queue[i]._load_queue_ptr_write = 0; // not necessary
130	_queue[i]._has_immediat = 0; // not necessary
131	_queue[i]._immediat = 0; // not necessary
132	// _queue[i]._read_ra = 0; // not necessary
133	_queue[i]._num_reg_ra = 0; // not necessary
134	_queue[i]._data_ra_val = 0; // not necessary
135	_queue[i]._data_ra = 0; // not necessary
136	// _queue[i]._read_rb = 0; // not necessary
137	_queue[i]._num_reg_rb = 0; // not necessary
138	_queue[i]._data_rb_val = 0; // not necessary
139	_queue[i]._data_rb = 0; // not necessary
140	// _queue[i]._read_rc = 0; // not necessary
141	_queue[i]._num_reg_rc = 0; // not necessary
142	_queue[i]._data_rc_val = 0; // not necessary
143	_queue[i]._data_rc = 0; // not necessary
144	_queue[i]._write_rd = 0; // not necessary
145	_queue[i]._num_reg_rd = 0; // not necessary
146	_queue[i]._write_re = 0; // not necessary
147	_queue[i]._num_reg_re = 0; // not necessary
148	}
149	}
150	else
151	{
152	// ***** POP from reservation station
153
154	// scan in reverse order, because when we pop the queue there are an auto reorder
155	//for (int32_t i=(static_cast<int32_t>(_queue_control->nb_elt()))-1;i>=0; i--)
156	for (int32_t i=(static_cast<int32_t>(_param->_nb_inst_retire))-1;i>=0; i--)
157	{
158	if (( internal_RETIRE_VAL [i] == 1) and
159	(PORT_READ(in_RETIRE_ACK [i]) == 1))
160	{
161	//uint32_t index = (*_queue_control)[i];
162
163	log_printf(NONE,Reservation_station,FUNCTION," * POP [%d]",i);
164
165	uint32_t index = internal_RETIRE_SLOT[i];
166
167	#ifdef SYSTEMC_VHDL_COMPATIBILITY
168	_queue_valid [index] = false;
169	#else
170	_queue_control->pop(index);
171	#endif
172	// cout << "========== Transition : " << endl
173	// << " * i : " << i << endl
174	// << " * index : " << index << endl;
175
176	log_printf(NONE,Reservation_station,FUNCTION," * index : %d",index);
177	}
178	}
179
180	// dump_queue();
181
182	// ***** Bypass
183	// Note : we can take this sequence code before the PUSH in the queue, because read_queue make the bypass !!!
184
185	// scan all entry
186	for (uint32_t i=0;
187	#ifdef SYSTEMC_VHDL_COMPATIBILITY
188	i<_param->_size_queue;
189	#else
190	i<_queue_control->nb_elt();
191	#endif
192	i++)
193	{
194	uint32_t index;
195	#ifdef SYSTEMC_VHDL_COMPATIBILITY
196	index = i;
197	#else
198	index = (*_queue_control)[i];
199	#endif
200
201	// ***** bypass - gpr_write
202	for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
203	{
204	bool cmp;
205	if (_param->_have_port_ooo_engine_id)
206	cmp = (PORT_READ(in_GPR_WRITE_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id);
207	else
208	cmp = true;
209
210	if ((PORT_READ(in_GPR_WRITE_VAL [j]) == 1) and cmp)
211	{
212	if (PORT_READ(in_GPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_ra)
213	{
214	log_printf(TRACE,Reservation_station,FUNCTION," -> GPR_WRITE [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra);
215	_queue[index]._data_ra_val = 1;
216	_queue[index]._data_ra = PORT_READ(in_GPR_WRITE_DATA [j]);
217	}
218	if (PORT_READ(in_GPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_rb)
219	{
220	log_printf(TRACE,Reservation_station,FUNCTION," -> GPR_WRITE [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb);
221	_queue[index]._data_rb_val = 1;
222	_queue[index]._data_rb = PORT_READ(in_GPR_WRITE_DATA [j]);
223	}
224	}
225	}
226	// ***** bypass - spr_write
227	for (uint32_t j=0; j<_param->_nb_spr_write; j++)
228	{
229	bool cmp;
230	if (_param->_have_port_ooo_engine_id)
231	cmp = (PORT_READ(in_SPR_WRITE_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id);
232	else
233	cmp = true;
234
235	if ((PORT_READ(in_SPR_WRITE_VAL [j]) == 1) and
236	cmp and
237	(PORT_READ(in_SPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_rc))
238	{
239	log_printf(TRACE,Reservation_station,FUNCTION," -> SPR_WRITE [%d] - Hit queue[%d]-SPR_RC[%d]",i,index,_queue[index]._num_reg_rc);
240	_queue[index]._data_rc_val = 1;
241	_queue[index]._data_rc = PORT_READ(in_SPR_WRITE_DATA [j]);
242	}
243	}
244	// ***** bypass - bypass_write
245	for (uint32_t j=0; j<_param->_nb_bypass_write; j++)
246	{
247	bool cmp;
248	if (_param->_have_port_ooo_engine_id)
249	cmp = (PORT_READ(in_BYPASS_WRITE_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id);
250	else
251	cmp = true;
252
253	if (cmp)
254	{
255	if (PORT_READ(in_BYPASS_WRITE_GPR_VAL [j]) == 1)
256	{
257	if (PORT_READ(in_BYPASS_WRITE_GPR_NUM_REG[j]) == _queue[index]._num_reg_ra)
258	{
259	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra);
260	_queue[index]._data_ra_val = 1;
261	_queue[index]._data_ra = PORT_READ(in_BYPASS_WRITE_GPR_DATA [j]);
262	}
263	if (PORT_READ(in_BYPASS_WRITE_GPR_NUM_REG [j]) == _queue[index]._num_reg_rb)
264	{
265	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb);
266	_queue[index]._data_rb_val = 1;
267	_queue[index]._data_rb = PORT_READ(in_BYPASS_WRITE_GPR_DATA [j]);
268	}
269	}
270	if ((PORT_READ(in_BYPASS_WRITE_SPR_VAL [j]) == 1) and
271	(PORT_READ(in_BYPASS_WRITE_SPR_NUM_REG[j]) == _queue[index]._num_reg_rc))
272	{
273	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-SPR_RC[%d]",i,index,_queue[index]._num_reg_rc);
274	_queue[index]._data_rc_val = 1;
275	_queue[index]._data_rc = PORT_READ(in_BYPASS_WRITE_SPR_DATA [j]);
276	}
277	}
278	}
279	// ***** bypass - bypass_memory
280	for (uint32_t j=0; j<_param->_nb_bypass_memory; j++)
281	{
282	bool cmp;
283	if (_param->_have_port_ooo_engine_id)
284	cmp = (PORT_READ(in_BYPASS_MEMORY_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id);
285	else
286	cmp = true;
287
288	if ((PORT_READ(in_BYPASS_MEMORY_VAL [j]) == 1) and cmp)
289	{
290	if (PORT_READ(in_BYPASS_MEMORY_NUM_REG [j]) == _queue[index]._num_reg_ra)
291	{
292	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_MEMORY [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra);
293	_queue[index]._data_ra_val = 1;
294	_queue[index]._data_ra = PORT_READ(in_BYPASS_MEMORY_DATA [j]);
295	}
296	if (PORT_READ(in_BYPASS_MEMORY_NUM_REG [j]) == _queue[index]._num_reg_rb)
297	{
298	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_MEMORY [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb);
299	_queue[index]._data_rb_val = 1;
300	_queue[index]._data_rb = PORT_READ(in_BYPASS_MEMORY_DATA [j]);
301	}
302	}
303	}
304	}
305	// ***** PUSH to reservation station
306	if ((PORT_READ(in_INSERT_VAL) == 1) and
307	( internal_INSERT_ACK == 1))
308	{
309	log_printf(TRACE,Reservation_station,FUNCTION," * PUSH");
310
311	// Write in reservation station
312	uint32_t index;
313
314	#ifdef SYSTEMC_VHDL_COMPATIBILITY
315	index = internal_INSERT_SLOT;
316	_queue_valid [internal_INSERT_SLOT] = true;
317	#else
318	index = _queue_control->push();
319	#endif
320	log_printf(TRACE,Reservation_station,FUNCTION," * index : %d",index);
321
322	if (_param->_have_port_context_id)
323	_queue[index]._context_id = PORT_READ(in_INSERT_CONTEXT_ID );
324	if (_param->_have_port_front_end_id)
325	_queue[index]._front_end_id = PORT_READ(in_INSERT_FRONT_END_ID );
326	if (_param->_have_port_ooo_engine_id)
327	_queue[index]._ooo_engine_id = PORT_READ(in_INSERT_OOO_ENGINE_ID );
328	if (_param->_have_port_rob_ptr)
329	_queue[index]._rob_id = PORT_READ(in_INSERT_ROB_ID );
330	_queue[index]._operation = PORT_READ(in_INSERT_OPERATION );
331	_queue[index]._type = PORT_READ(in_INSERT_TYPE );
332	_queue[index]._cancel = PORT_READ(in_INSERT_CANCEL );
333	_queue[index]._store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE);
334	_queue[index]._store_queue_ptr_read = PORT_READ(in_INSERT_STORE_QUEUE_PTR_READ );
335	_queue[index]._store_queue_empty = PORT_READ(in_INSERT_STORE_QUEUE_EMPTY );
336	if (_param->_have_port_load_queue_ptr)
337	_queue[index]._load_queue_ptr_write = PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE );
338	_queue[index]._has_immediat = PORT_READ(in_INSERT_HAS_IMMEDIAT );
339	_queue[index]._immediat = PORT_READ(in_INSERT_IMMEDIAT );
340	// _queue[index]._read_ra = PORT_READ(in_INSERT_READ_RA );
341	_queue[index]._num_reg_ra = PORT_READ(in_INSERT_NUM_REG_RA );
342	_queue[index]._data_ra_val = PORT_READ(in_INSERT_DATA_RA_VAL );
343	_queue[index]._data_ra = PORT_READ(in_INSERT_DATA_RA );
344	// _queue[index]._read_rb = PORT_READ(in_INSERT_READ_RB );
345	_queue[index]._num_reg_rb = PORT_READ(in_INSERT_NUM_REG_RB );
346	_queue[index]._data_rb_val = PORT_READ(in_INSERT_DATA_RB_VAL );
347	_queue[index]._data_rb = PORT_READ(in_INSERT_DATA_RB );
348	// _queue[index]._read_rc = PORT_READ(in_INSERT_READ_RC );
349	_queue[index]._num_reg_rc = PORT_READ(in_INSERT_NUM_REG_RC );
350	_queue[index]._data_rc_val = PORT_READ(in_INSERT_DATA_RC_VAL );
351	_queue[index]._data_rc = PORT_READ(in_INSERT_DATA_RC );
352	_queue[index]._write_rd = PORT_READ(in_INSERT_WRITE_RD );
353	_queue[index]._num_reg_rd = PORT_READ(in_INSERT_NUM_REG_RD );
354	_queue[index]._write_re = PORT_READ(in_INSERT_WRITE_RE );
355	_queue[index]._num_reg_re = PORT_READ(in_INSERT_NUM_REG_RE );
356	// dump_queue();
357	}
358	}
359
360	dump_queue();
361
362	end_cycle ();
363
364	log_end(Reservation_station,FUNCTION);
365	};
366
367	}; // end namespace reservation_station
368	}; // end namespace read_unit
369	}; // end namespace multi_read_unit
370	}; // end namespace execute_loop
371	}; // end namespace multi_execute_loop
372	}; // end namespace core
373
374	}; // end namespace behavioural
375	}; // end namespace morpheo
376	#endif
377	//#endif

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