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Reservation_station_transition.cpp @ 146

Last change on this file since 146 was 146, checked in by rosiere, 13 years ago
1) Integration of RegisterFile_Internal_Banked in RegisterFile? 2) Erase "read_write" interface in RegisterFile_Monolithic component 3) Add smith predictor parameters in Load_store_pointer_unit. 4) Fix not statistics flags
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1	#ifdef SYSTEMC
2	/*
3	* $Id: Reservation_station_transition.cpp 146 2011-02-01 20:57:54Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_execute_loop {
15	namespace execute_loop {
16	namespace multi_read_unit {
17	namespace read_unit {
18	namespace reservation_station {
19
20	#ifdef SYSTEMC_VHDL_COMPATIBILITY
21	#define dump_queue() \
22	do \
23	{ \
24	log_printf(TRACE,Reservation_station,FUNCTION," * Dump Reservation Station"); \
25	for (uint32_t it_dump=0;it_dump<_param->_size_queue; it_dump++) \
26	if (_queue_valid [it_dump]) \
27	log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d %.1d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \
28	it_dump, \
29	_queue[it_dump]._context_id , \
30	_queue[it_dump]._front_end_id , \
31	_queue[it_dump]._ooo_engine_id , \
32	_queue[it_dump]._rob_id , \
33	_queue[it_dump]._type , \
34	_queue[it_dump]._operation , \
35	_queue[it_dump]._cancel , \
36	_queue[it_dump]._store_queue_ptr_write, \
37	_queue[it_dump]._store_queue_ptr_read , \
38	_queue[it_dump]._store_queue_empty , \
39	_queue[it_dump]._load_queue_ptr_write , \
40	_queue[it_dump]._has_immediat , \
41	_queue[it_dump]._immediat , \
42	_queue[it_dump]._num_reg_ra , \
43	_queue[it_dump]._data_ra_val , \
44	_queue[it_dump]._data_ra , \
45	_queue[it_dump]._num_reg_rb , \
46	_queue[it_dump]._data_rb_val , \
47	_queue[it_dump]._data_rb , \
48	_queue[it_dump]._num_reg_rc , \
49	_queue[it_dump]._data_rc_val , \
50	_queue[it_dump]._data_rc , \
51	_queue[it_dump]._write_rd , \
52	_queue[it_dump]._num_reg_rd , \
53	_queue[it_dump]._write_re , \
54	_queue[it_dump]._num_reg_re , \
55	toString(_queue[it_dump]._type).c_str()); \
56	} while (0)
57	#else
58	#define dump_queue() \
59	do \
60	{ \
61	log_printf(TRACE,Reservation_station,FUNCTION," * Dump Reservation Station"); \
62	log_printf(TRACE,Reservation_station,FUNCTION," * nb_elt : %d",_queue_control->nb_elt()); \
63	for (uint32_t it_dump=0;it_dump<_param->_size_queue; it_dump++) \
64	if (it_dump < _queue_control->nb_elt()) \
65	log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d %.1d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \
66	(*_queue_control)[it_dump], \
67	_queue[(*_queue_control)[it_dump]]._context_id , \
68	_queue[(*_queue_control)[it_dump]]._front_end_id , \
69	_queue[(*_queue_control)[it_dump]]._ooo_engine_id , \
70	_queue[(*_queue_control)[it_dump]]._rob_id , \
71	_queue[(*_queue_control)[it_dump]]._type , \
72	_queue[(*_queue_control)[it_dump]]._operation , \
73	_queue[(*_queue_control)[it_dump]]._cancel , \
74	_queue[(*_queue_control)[it_dump]]._store_queue_ptr_write, \
75	_queue[(*_queue_control)[it_dump]]._store_queue_ptr_read , \
76	_queue[(*_queue_control)[it_dump]]._store_queue_empty , \
77	_queue[(*_queue_control)[it_dump]]._load_queue_ptr_write , \
78	_queue[(*_queue_control)[it_dump]]._has_immediat , \
79	_queue[(*_queue_control)[it_dump]]._immediat , \
80	_queue[(*_queue_control)[it_dump]]._num_reg_ra , \
81	_queue[(*_queue_control)[it_dump]]._data_ra_val , \
82	_queue[(*_queue_control)[it_dump]]._data_ra , \
83	_queue[(*_queue_control)[it_dump]]._num_reg_rb , \
84	_queue[(*_queue_control)[it_dump]]._data_rb_val , \
85	_queue[(*_queue_control)[it_dump]]._data_rb , \
86	_queue[(*_queue_control)[it_dump]]._num_reg_rc , \
87	_queue[(*_queue_control)[it_dump]]._data_rc_val , \
88	_queue[(*_queue_control)[it_dump]]._data_rc , \
89	_queue[(*_queue_control)[it_dump]]._write_rd , \
90	_queue[(*_queue_control)[it_dump]]._num_reg_rd , \
91	_queue[(*_queue_control)[it_dump]]._write_re , \
92	_queue[(*_queue_control)[it_dump]]._num_reg_re , \
93	toString(_queue[(*_queue_control)[it_dump]]._type).c_str()); \
94	else \
95	log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d]", \
96	(*_queue_control)[it_dump]); \
97	} while (0)
98	#endif
99
100	#undef FUNCTION
101	#define FUNCTION "Reservation_station::transition"
102	void Reservation_station::transition (void)
103	{
104	log_begin(Reservation_station,FUNCTION);
105	log_function(Reservation_station,FUNCTION,_name.c_str());
106
107	if (PORT_READ(in_NRESET) == 0)
108	{
109	#ifdef SYSTEMC_VHDL_COMPATIBILITY
110	for (uint32_t i=0; i<_param->_size_queue; i++)
111	_queue_valid [i] = false;
112	#else
113	_queue_control->clear();
114	#endif
115
116	for (uint32_t i=0; i<_param->_size_queue; i++)
117	{
118	_queue[i]._context_id = 0; // not necessary
119	_queue[i]._front_end_id = 0; // not necessary
120	_queue[i]._ooo_engine_id = 0; // not necessary
121	_queue[i]._rob_id = 0; // not necessary
122	_queue[i]._operation = 0; // not necessary
123	_queue[i]._type = 0; // not necessary
124	_queue[i]._cancel = 0; // not necessary
125	_queue[i]._store_queue_ptr_write = 0; // not necessary
126	_queue[i]._store_queue_ptr_read = 0; // not necessary
127	_queue[i]._store_queue_empty = 0; // not necessary
128	_queue[i]._load_queue_ptr_write = 0; // not necessary
129	_queue[i]._has_immediat = 0; // not necessary
130	_queue[i]._immediat = 0; // not necessary
131	// _queue[i]._read_ra = 0; // not necessary
132	_queue[i]._num_reg_ra = 0; // not necessary
133	_queue[i]._data_ra_val = 0; // not necessary
134	_queue[i]._data_ra = 0; // not necessary
135	// _queue[i]._read_rb = 0; // not necessary
136	_queue[i]._num_reg_rb = 0; // not necessary
137	_queue[i]._data_rb_val = 0; // not necessary
138	_queue[i]._data_rb = 0; // not necessary
139	// _queue[i]._read_rc = 0; // not necessary
140	_queue[i]._num_reg_rc = 0; // not necessary
141	_queue[i]._data_rc_val = 0; // not necessary
142	_queue[i]._data_rc = 0; // not necessary
143	_queue[i]._write_rd = 0; // not necessary
144	_queue[i]._num_reg_rd = 0; // not necessary
145	_queue[i]._write_re = 0; // not necessary
146	_queue[i]._num_reg_re = 0; // not necessary
147	}
148	}
149	else
150	{
151	// ***** POP from reservation station
152
153	// scan in reverse order, because when we pop the queue there are an auto reorder
154	//for (int32_t i=(static_cast<int32_t>(_queue_control->nb_elt()))-1;i>=0; i--)
155	for (int32_t i=(static_cast<int32_t>(_param->_nb_inst_retire))-1;i>=0; i--)
156	{
157	if (( internal_RETIRE_VAL [i] == 1) and
158	(PORT_READ(in_RETIRE_ACK [i]) == 1))
159	{
160	//uint32_t index = (*_queue_control)[i];
161
162	log_printf(NONE,Reservation_station,FUNCTION," * POP [%d]",i);
163
164	uint32_t index = internal_RETIRE_SLOT[i];
165
166	#ifdef SYSTEMC_VHDL_COMPATIBILITY
167	_queue_valid [index] = false;
168	#else
169	_queue_control->pop(index);
170	#endif
171	// cout << "========== Transition : " << endl
172	// << " * i : " << i << endl
173	// << " * index : " << index << endl;
174
175	log_printf(NONE,Reservation_station,FUNCTION," * index : %d",index);
176	}
177	}
178
179	// dump_queue();
180
181	// ***** Bypass
182	// Note : we can take this sequence code before the PUSH in the queue, because read_queue make the bypass !!!
183
184	// scan all entry
185	for (uint32_t i=0;
186	#ifdef SYSTEMC_VHDL_COMPATIBILITY
187	i<_param->_size_queue;
188	#else
189	i<_queue_control->nb_elt();
190	#endif
191	i++)
192	{
193	uint32_t index;
194	#ifdef SYSTEMC_VHDL_COMPATIBILITY
195	index = i;
196	#else
197	index = (*_queue_control)[i];
198	#endif
199
200	// ***** bypass - gpr_write
201	for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
202	{
203	bool cmp;
204	if (_param->_have_port_ooo_engine_id)
205	cmp = (PORT_READ(in_GPR_WRITE_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id);
206	else
207	cmp = true;
208
209	if ((PORT_READ(in_GPR_WRITE_VAL [j]) == 1) and cmp)
210	{
211	if (PORT_READ(in_GPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_ra)
212	{
213	log_printf(TRACE,Reservation_station,FUNCTION," -> GPR_WRITE [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra);
214	_queue[index]._data_ra_val = 1;
215	_queue[index]._data_ra = PORT_READ(in_GPR_WRITE_DATA [j]);
216	}
217	if (PORT_READ(in_GPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_rb)
218	{
219	log_printf(TRACE,Reservation_station,FUNCTION," -> GPR_WRITE [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb);
220	_queue[index]._data_rb_val = 1;
221	_queue[index]._data_rb = PORT_READ(in_GPR_WRITE_DATA [j]);
222	}
223	}
224	}
225	// ***** bypass - spr_write
226	for (uint32_t j=0; j<_param->_nb_spr_write; j++)
227	{
228	bool cmp;
229	if (_param->_have_port_ooo_engine_id)
230	cmp = (PORT_READ(in_SPR_WRITE_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id);
231	else
232	cmp = true;
233
234	if ((PORT_READ(in_SPR_WRITE_VAL [j]) == 1) and
235	cmp and
236	(PORT_READ(in_SPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_rc))
237	{
238	log_printf(TRACE,Reservation_station,FUNCTION," -> SPR_WRITE [%d] - Hit queue[%d]-SPR_RC[%d]",i,index,_queue[index]._num_reg_rc);
239	_queue[index]._data_rc_val = 1;
240	_queue[index]._data_rc = PORT_READ(in_SPR_WRITE_DATA [j]);
241	}
242	}
243	// ***** bypass - bypass_write
244	for (uint32_t j=0; j<_param->_nb_bypass_write; j++)
245	{
246	bool cmp;
247	if (_param->_have_port_ooo_engine_id)
248	cmp = (PORT_READ(in_BYPASS_WRITE_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id);
249	else
250	cmp = true;
251
252	if (cmp)
253	{
254	if (PORT_READ(in_BYPASS_WRITE_GPR_VAL [j]) == 1)
255	{
256	if (PORT_READ(in_BYPASS_WRITE_GPR_NUM_REG[j]) == _queue[index]._num_reg_ra)
257	{
258	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra);
259	_queue[index]._data_ra_val = 1;
260	_queue[index]._data_ra = PORT_READ(in_BYPASS_WRITE_GPR_DATA [j]);
261	}
262	if (PORT_READ(in_BYPASS_WRITE_GPR_NUM_REG [j]) == _queue[index]._num_reg_rb)
263	{
264	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb);
265	_queue[index]._data_rb_val = 1;
266	_queue[index]._data_rb = PORT_READ(in_BYPASS_WRITE_GPR_DATA [j]);
267	}
268	}
269	if ((PORT_READ(in_BYPASS_WRITE_SPR_VAL [j]) == 1) and
270	(PORT_READ(in_BYPASS_WRITE_SPR_NUM_REG[j]) == _queue[index]._num_reg_rc))
271	{
272	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-SPR_RC[%d]",i,index,_queue[index]._num_reg_rc);
273	_queue[index]._data_rc_val = 1;
274	_queue[index]._data_rc = PORT_READ(in_BYPASS_WRITE_SPR_DATA [j]);
275	}
276	}
277	}
278	// ***** bypass - bypass_memory
279	for (uint32_t j=0; j<_param->_nb_bypass_memory; j++)
280	{
281	bool cmp;
282	if (_param->_have_port_ooo_engine_id)
283	cmp = (PORT_READ(in_BYPASS_MEMORY_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id);
284	else
285	cmp = true;
286
287	if ((PORT_READ(in_BYPASS_MEMORY_VAL [j]) == 1) and cmp)
288	{
289	if (PORT_READ(in_BYPASS_MEMORY_NUM_REG [j]) == _queue[index]._num_reg_ra)
290	{
291	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_MEMORY [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra);
292	_queue[index]._data_ra_val = 1;
293	_queue[index]._data_ra = PORT_READ(in_BYPASS_MEMORY_DATA [j]);
294	}
295	if (PORT_READ(in_BYPASS_MEMORY_NUM_REG [j]) == _queue[index]._num_reg_rb)
296	{
297	log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_MEMORY [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb);
298	_queue[index]._data_rb_val = 1;
299	_queue[index]._data_rb = PORT_READ(in_BYPASS_MEMORY_DATA [j]);
300	}
301	}
302	}
303	}
304	// ***** PUSH to reservation station
305	if ((PORT_READ(in_INSERT_VAL) == 1) and
306	( internal_INSERT_ACK == 1))
307	{
308	log_printf(TRACE,Reservation_station,FUNCTION," * PUSH");
309
310	// Write in reservation station
311	uint32_t index;
312
313	#ifdef SYSTEMC_VHDL_COMPATIBILITY
314	index = internal_INSERT_SLOT;
315	_queue_valid [internal_INSERT_SLOT] = true;
316	#else
317	index = _queue_control->push();
318	#endif
319	log_printf(TRACE,Reservation_station,FUNCTION," * index : %d",index);
320
321	if (_param->_have_port_context_id)
322	_queue[index]._context_id = PORT_READ(in_INSERT_CONTEXT_ID );
323	if (_param->_have_port_front_end_id)
324	_queue[index]._front_end_id = PORT_READ(in_INSERT_FRONT_END_ID );
325	if (_param->_have_port_ooo_engine_id)
326	_queue[index]._ooo_engine_id = PORT_READ(in_INSERT_OOO_ENGINE_ID );
327	if (_param->_have_port_rob_ptr)
328	_queue[index]._rob_id = PORT_READ(in_INSERT_ROB_ID );
329	_queue[index]._operation = PORT_READ(in_INSERT_OPERATION );
330	_queue[index]._type = PORT_READ(in_INSERT_TYPE );
331	_queue[index]._cancel = PORT_READ(in_INSERT_CANCEL );
332	_queue[index]._store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE);
333	_queue[index]._store_queue_ptr_read = PORT_READ(in_INSERT_STORE_QUEUE_PTR_READ );
334	_queue[index]._store_queue_empty = PORT_READ(in_INSERT_STORE_QUEUE_EMPTY );
335	if (_param->_have_port_load_queue_ptr)
336	_queue[index]._load_queue_ptr_write = PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE );
337	_queue[index]._has_immediat = PORT_READ(in_INSERT_HAS_IMMEDIAT );
338	_queue[index]._immediat = PORT_READ(in_INSERT_IMMEDIAT );
339	// _queue[index]._read_ra = PORT_READ(in_INSERT_READ_RA );
340	_queue[index]._num_reg_ra = PORT_READ(in_INSERT_NUM_REG_RA );
341	_queue[index]._data_ra_val = PORT_READ(in_INSERT_DATA_RA_VAL );
342	_queue[index]._data_ra = PORT_READ(in_INSERT_DATA_RA );
343	// _queue[index]._read_rb = PORT_READ(in_INSERT_READ_RB );
344	_queue[index]._num_reg_rb = PORT_READ(in_INSERT_NUM_REG_RB );
345	_queue[index]._data_rb_val = PORT_READ(in_INSERT_DATA_RB_VAL );
346	_queue[index]._data_rb = PORT_READ(in_INSERT_DATA_RB );
347	// _queue[index]._read_rc = PORT_READ(in_INSERT_READ_RC );
348	_queue[index]._num_reg_rc = PORT_READ(in_INSERT_NUM_REG_RC );
349	_queue[index]._data_rc_val = PORT_READ(in_INSERT_DATA_RC_VAL );
350	_queue[index]._data_rc = PORT_READ(in_INSERT_DATA_RC );
351	_queue[index]._write_rd = PORT_READ(in_INSERT_WRITE_RD );
352	_queue[index]._num_reg_rd = PORT_READ(in_INSERT_NUM_REG_RD );
353	_queue[index]._write_re = PORT_READ(in_INSERT_WRITE_RE );
354	_queue[index]._num_reg_re = PORT_READ(in_INSERT_NUM_REG_RE );
355	// dump_queue();
356	}
357	}
358
359	dump_queue();
360
361	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
362	end_cycle ();
363	#endif
364
365	log_end(Reservation_station,FUNCTION);
366	};
367
368	}; // end namespace reservation_station
369	}; // end namespace read_unit
370	}; // end namespace multi_read_unit
371	}; // end namespace execute_loop
372	}; // end namespace multi_execute_loop
373	}; // end namespace core
374
375	}; // end namespace behavioural
376	}; // end namespace morpheo
377	#endif

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp @ 146

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