source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp @ 103

#ifdef SYSTEMC
/*
 * $Id: Write_queue_genMoore.cpp 103 2009-01-16 16:55:32Z moulu $
 *
 * [ Description ]
 * 
 */

#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h"

namespace morpheo                    {
namespace behavioural {
namespace core {
namespace multi_execute_loop {
namespace execute_loop {
namespace multi_write_unit {
namespace write_unit {
namespace write_queue {


#undef  FUNCTION
#define FUNCTION "Write_queue::genMoore"
  void Write_queue::genMoore (void)
  {
    log_begin(Write_queue,FUNCTION);
    log_function(Write_queue,FUNCTION,_name.c_str());
    
    // -----[ Interface "Write_queue_in" ]--------------------------------
    {
      internal_WRITE_QUEUE_IN_ACK = _queue->size() < _param->_size_queue;
      
      PORT_WRITE(out_WRITE_QUEUE_IN_ACK, internal_WRITE_QUEUE_IN_ACK);
    }

    // -----[ Interface "Write_queue_out" ]--------------------------------
    {
      // TODO : make a genMealy version
      internal_WRITE_QUEUE_OUT_VAL = ((not _queue->empty()           ) and
                                      (not _queue->front()->_write_rd) and
                                      (not _queue->front()->_write_re));
      
      PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL);

      if (internal_WRITE_QUEUE_OUT_VAL)
        {
          if (_param->_have_port_context_id)
          PORT_WRITE(out_WRITE_QUEUE_OUT_CONTEXT_ID   , _queue->front()->_context_id   );
          if (_param->_have_port_front_end_id)
          PORT_WRITE(out_WRITE_QUEUE_OUT_FRONT_END_ID , _queue->front()->_front_end_id );
          if (_param->_have_port_ooo_engine_id)
          PORT_WRITE(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID, _queue->front()->_ooo_engine_id);
          if (_param->_have_port_rob_ptr  )
          PORT_WRITE(out_WRITE_QUEUE_OUT_PACKET_ID    , _queue->front()->_packet_id    );
//        PORT_WRITE(out_WRITE_QUEUE_OUT_OPERATION    , _queue->front()->_operation    );
//        PORT_WRITE(out_WRITE_QUEUE_OUT_TYPE         , _queue->front()->_type         );
          PORT_WRITE(out_WRITE_QUEUE_OUT_FLAGS        , _queue->front()->_data_re      );
          PORT_WRITE(out_WRITE_QUEUE_OUT_EXCEPTION    , _queue->front()->_exception    );
          PORT_WRITE(out_WRITE_QUEUE_OUT_NO_SEQUENCE  , _queue->front()->_no_sequence  );
          PORT_WRITE(out_WRITE_QUEUE_OUT_ADDRESS      , _queue->front()->_address      );
          PORT_WRITE(out_WRITE_QUEUE_OUT_DATA         , _queue->front()->_data_rd      );
        }
    }

    // -----[ Interface "gpr_write" ]-------------------------------------
    // -----[ Interface "spr_write" ]-------------------------------------
    {
      bool val = not _queue->empty();

      internal_GPR_WRITE_VAL = val and _queue->front()->_write_rd;
      internal_SPR_WRITE_VAL = val and _queue->front()->_write_re;
      
      PORT_WRITE(out_GPR_WRITE_VAL [0], internal_GPR_WRITE_VAL);
      PORT_WRITE(out_SPR_WRITE_VAL [0], internal_SPR_WRITE_VAL);

      if (val)
        {
          if (_param->_have_port_ooo_engine_id)
          {
          PORT_WRITE(out_GPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id);
          PORT_WRITE(out_SPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id);
          }
          PORT_WRITE(out_GPR_WRITE_NUM_REG       [0], _queue->front()->_num_reg_rd);
          PORT_WRITE(out_GPR_WRITE_DATA          [0], _queue->front()->_data_rd   );
          PORT_WRITE(out_SPR_WRITE_NUM_REG       [0], _queue->front()->_num_reg_re);
          PORT_WRITE(out_SPR_WRITE_DATA          [0], _queue->front()->_data_re   );
        }
    }
    // -----[ Interface "bypass_write" ]----------------------------------
    {
      std::list<write_queue_entry_t *>::iterator it = _queue->begin();
      for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
        {
          bool val     = i < _queue->size();
          
          if (val)
            {
              if (_param->_have_port_ooo_engine_id)
              PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [i], (*it)->_ooo_engine_id);
              PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [i], (*it)->_num_reg_rd);
              PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [i], (*it)->_data_rd   );
              PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [i], (*it)->_num_reg_re);
              PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [i], (*it)->_data_re   );
            }
#ifdef SYSTEMC_VHDL_COMPATIBILITY
          else
            {
              if (_param->_have_port_ooo_engine_id)
              PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [i], 0);
              PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [i], 0);
              PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [i], 0);
              PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [i], 0);
              PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [i], 0);
            }
#endif

          PORT_WRITE(out_BYPASS_WRITE_GPR_VAL       [i], val and (*it)->_write_rd  );
          PORT_WRITE(out_BYPASS_WRITE_SPR_VAL       [i], val and (*it)->_write_re  );
          
          if (it != _queue->end())
            it++;
        }
    }
    log_end(Write_queue,FUNCTION);
  };

}; // end namespace write_queue
}; // end namespace write_unit
}; // end namespace multi_write_unit
}; // end namespace execute_loop
}; // end namespace multi_execute_loop
}; // end namespace core

}; // end namespace behavioural
}; // end namespace morpheo              
#endif