Changeset 103
- Timestamp:
- Jan 16, 2009, 5:55:32 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo
- Files:
-
- 16 edited
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/Makefile.deps (modified) (4 diffs)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Parameters.h (modified) (1 diff)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp (modified) (2 diffs)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp (modified) (1 diff)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_vhdl.cpp (modified) (2 diffs)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_vhdl_body.cpp (modified) (1 diff)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_vhdl_declaration.cpp (modified) (2 diffs)
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Behavioural/Generic/Queue/include/Queue.h (modified) (1 diff)
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Behavioural/Generic/Queue/src/Queue_vhdl_body.cpp (modified) (2 diffs)
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Behavioural/Generic/Queue/src/Queue_vhdl_declaration.cpp (modified) (1 diff)
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Behavioural/Makefile.Common (modified) (1 diff)
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Behavioural/Makefile.Synthesis (modified) (2 diffs)
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Behavioural/Makefile.mkf (modified) (3 diffs)
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Behavioural/include/Version.h (modified) (1 diff)
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Behavioural/mkf.info (modified) (1 diff)
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Common/include/ToBase2.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/Makefile.deps
r81 r103 13 13 include $(DIR_MORPHEO)/Behavioural/Makefile.deps 14 14 endif 15 ifndef Queue 16 include $(DIR_MORPHEO)/Behavioural/Generic/Queue/Makefile.deps 17 endif 15 18 16 19 #-----[ Directory ]---------------------------------------- … … 21 24 22 25 Write_queue_LIBRARY = -lWrite_queue \ 26 $(Queue_LIBRARY) \ 23 27 $(Behavioural_LIBRARY) 24 28 25 29 Write_queue_DIR_LIBRARY = -L$(Write_queue_DIR)/lib \ 30 $(Queue_DIR_LIBRARY) \ 26 31 $(Behavioural_DIR_LIBRARY) 27 32 … … 30 35 Write_queue_library : 31 36 @\ 37 $(MAKE) Queue_library; \ 32 38 $(MAKE) Behavioural_library; \ 33 39 $(MAKE) --directory=$(Write_queue_DIR) --makefile=Makefile; … … 35 41 Write_queue_library_clean : 36 42 @\ 43 $(MAKE) Queue_library_clean; \ 37 44 $(MAKE) Behavioural_library_clean; \ 38 45 $(MAKE) --directory=$(Write_queue_DIR) --makefile=Makefile clean; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Parameters.h
r88 r103 46 46 //public : uint32_t _size_general_register ; 47 47 //public : uint32_t _size_special_register ; 48 public : uint32_t _size_internal_queue ; 48 49 49 50 //public : bool _have_port_context_id ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp
r97 r103 47 47 48 48 test(); 49 49 50 50 if (is_toplevel) 51 51 { … … 67 67 copy(); 68 68 } 69 70 _size_internal_queue = 71 ( _size_context_id + 72 _size_front_end_id + 73 _size_ooo_engine_id + 74 _size_rob_ptr + 75 1 + 76 _size_general_register + 77 _size_general_data + 78 1 + 79 _size_special_register + 80 _size_special_data + 81 _size_exception + 82 1 + 83 _size_instruction_address 84 ); 69 85 70 86 log_printf(FUNC,Write_queue,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp
r101 r103 101 101 PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG [i], (*it)->_num_reg_re); 102 102 PORT_WRITE(out_BYPASS_WRITE_SPR_DATA [i], (*it)->_data_re ); 103 PORT_WRITE(out_BYPASS_WRITE_SPR_DATA [i], (*it)->_data_re );104 103 } 104 #ifdef SYSTEMC_VHDL_COMPATIBILITY 105 else 106 { 107 if (_param->_have_port_ooo_engine_id) 108 PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [i], 0); 109 PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG [i], 0); 110 PORT_WRITE(out_BYPASS_WRITE_GPR_DATA [i], 0); 111 PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG [i], 0); 112 PORT_WRITE(out_BYPASS_WRITE_SPR_DATA [i], 0); 113 } 114 #endif 115 105 116 PORT_WRITE(out_BYPASS_WRITE_GPR_VAL [i], val and (*it)->_write_rd ); 106 117 PORT_WRITE(out_BYPASS_WRITE_SPR_VAL [i], val and (*it)->_write_re ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_vhdl.cpp
r81 r103 9 9 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h" 10 10 #include "Behavioural/include/Vhdl.h" 11 #include "Behavioural/Generic/Queue/include/Queue.h" 11 12 12 13 namespace morpheo { … … 25 26 { 26 27 log_printf(FUNC,Write_queue,FUNCTION,"Begin"); 28 29 morpheo::behavioural::generic::queue::Parameters * param_queue; 30 morpheo::behavioural::generic::queue::Queue * queue; 31 32 param_queue = new morpheo::behavioural::generic::queue::Parameters 33 (_param->_size_queue, 34 _param->_size_internal_queue, 35 _param->_nb_bypass_write 36 ); 37 38 std::cout << "size internal queue :" << _param->_size_internal_queue << "." << std::endl; 39 40 std::string queue_name = _name + "_queue"; 41 queue = new morpheo::behavioural::generic::queue::Queue 42 (queue_name.c_str() 43 #ifdef STATISTICS 44 ,NULL 45 #endif 46 ,param_queue 47 ,USE_VHDL); 48 49 _component->set_component(queue->_component 50 #ifdef POSITION 51 , 50, 50, 50, 50 52 #endif 53 , INSTANCE_LIBRARY 54 ); 55 56 27 57 28 58 Vhdl * vhdl = new Vhdl (_name); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_vhdl_body.cpp
r81 r103 25 25 log_printf(FUNC,Write_queue,FUNCTION,"Begin"); 26 26 vhdl->set_body (""); 27 vhdl->set_comment(0,""); 28 vhdl->set_comment(0,"-----------------------------------"); 29 vhdl->set_comment(0,"-- Instance queue "); 30 vhdl->set_comment(0,"-----------------------------------"); 31 vhdl->set_comment(0,""); 32 33 vhdl->set_body (0,"instance_"+_name+"_queue : "+_name+"_queue"); 34 vhdl->set_body (0,"port map ("); 35 vhdl->set_body (1," in_CLOCK \t=>\t in_CLOCK "); 36 vhdl->set_body (1,", in_NRESET \t=>\t in_NRESET"); 37 vhdl->set_body (1,", in_INSERT_VAL \t=>\tsig_QUEUE_INSERT_VAL"); 38 vhdl->set_body (1,",out_INSERT_ACK \t=>\tsig_QUEUE_INSERT_ACK"); 39 vhdl->set_body (1,", in_INSERT_DATA \t=>\tsig_QUEUE_INSERT_DATA"); 40 vhdl->set_body (1,",out_RETIRE_VAL \t=>\tsig_QUEUE_RETIRE_VAL"); 41 vhdl->set_body (1,", in_RETIRE_ACK \t=>\tsig_QUEUE_RETIRE_ACK"); 42 vhdl->set_body (1,",out_RETIRE_DATA \t=>\tsig_QUEUE_RETIRE_DATA"); 43 for (uint32_t i=0; i<_param->_nb_bypass_write; i++) 44 { 45 vhdl->set_body (1,",out_SLOT_"+toString(i)+"_VAL \t=>\tsig_QUEUE_SLOT_"+toString(i)+"_VAL"); 46 vhdl->set_body (1,",out_SLOT_"+toString(i)+"_DATA \t=>\tsig_QUEUE_SLOT_"+toString(i)+"_DATA"); 47 } 48 vhdl->set_body (0,");"); 49 50 vhdl->set_body (0,""); 51 52 53 vhdl->set_comment(0,""); 54 vhdl->set_comment(0,"-----------------------------------"); 55 vhdl->set_comment(0,"-- Insides "); 56 vhdl->set_comment(0,"-----------------------------------"); 57 vhdl->set_comment(0,""); 58 59 vhdl->set_body (0,"write_rd_re_bis: process (in_CLOCK)"); 60 vhdl->set_body (0,"begin -- process write rd/re bis"); 61 vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); 62 // #ifdef SYSTEMC_VHDL_COMPATIBILITY 63 // vhdl->set_body (2,"if (in_NRESET = '0') then"); 64 // vhdl->set_body (2,"reg_GPR_WRITE <= '0';"); 65 // vhdl->set_body (2,"reg_SPR_WRITE <= '0';"); 66 // vhdl->set_body (2,"else"); 67 // #endif 68 vhdl->set_body (2,"reg_UPDATE <= (in_WRITE_QUEUE_OUT_ACK and sig_WRITE_QUEUE_OUT_VAL) or (not sig_QUEUE_RETIRE_VAL);"); 69 70 vhdl->set_body (2,"if (sig_GPR_WRITE_0_VAL = '1' and in_GPR_WRITE_0_ACK = '1') then"); 71 vhdl->set_body (3,"reg_GPR_WRITE <= '0';"); 72 vhdl->set_body (2,"else"); 73 vhdl->set_body (3,"reg_GPR_WRITE <= sig_GPR_WRITE;"); 74 vhdl->set_body (2,"end if;"); 75 76 vhdl->set_body (2,"if (sig_SPR_WRITE_0_VAL = '1' and in_SPR_WRITE_0_ACK = '1') then"); 77 vhdl->set_body (3,"reg_SPR_WRITE <= '0';"); 78 vhdl->set_body (2,"else"); 79 vhdl->set_body (3,"reg_SPR_WRITE <= sig_SPR_WRITE;"); 80 vhdl->set_body (2,"end if;"); 81 82 // #ifdef SYSTEMC_VHDL_COMPATIBILITY 83 // vhdl->set_body (2,"end if;"); 84 // #endif 85 vhdl->set_body (1,"end if;"); 86 vhdl->set_body (0,"end process write_rd_re_bis;"); 87 88 vhdl->set_body (0,"sig_GPR_WRITE <= sig_WRITE_RD when (reg_UPDATE = '1') else reg_GPR_WRITE;"); 89 vhdl->set_body (0,"sig_SPR_WRITE <= sig_WRITE_RE when (reg_UPDATE = '1') else reg_SPR_WRITE;"); 90 vhdl->set_body (0,"sig_GPR_WRITE_0_VAL <= sig_QUEUE_RETIRE_VAL and sig_GPR_WRITE;"); 91 vhdl->set_body (0,"sig_SPR_WRITE_0_VAL <= sig_QUEUE_RETIRE_VAL and sig_SPR_WRITE;"); 92 vhdl->set_body (0,"sig_DELETE_QUEUE_FRONT <= sig_QUEUE_RETIRE_VAL and not sig_GPR_WRITE and not sig_SPR_WRITE when (sig_WRITE_QUEUE_OUT_EXCEPTION = "+toString(EXCEPTION_MEMORY_LOAD_SPECULATIVE)+") else '0';"); 93 vhdl->set_body (0,"sig_WRITE_QUEUE_OUT_VAL <= sig_QUEUE_RETIRE_VAL and not sig_DELETE_QUEUE_FRONT and not sig_GPR_WRITE and not sig_SPR_WRITE;"); 94 vhdl->set_body (0,"sig_QUEUE_RETIRE_ACK <= sig_DELETE_QUEUE_FRONT or (in_WRITE_QUEUE_OUT_ACK and sig_WRITE_QUEUE_OUT_VAL);"); 95 96 if (_param->_nb_bypass_write > 0) 97 { 98 vhdl->set_body (0,"sig_BYPASS_WRITE_0_GPR_VAL <= sig_GPR_WRITE_0_VAL;"); 99 vhdl->set_body (0,"sig_BYPASS_WRITE_0_SPR_VAL <= sig_SPR_WRITE_0_VAL;"); 100 } 101 102 for (uint32_t i=1; i<_param->_nb_bypass_write; i++) 103 { 104 vhdl->set_body (0,"sig_BYPASS_WRITE_"+toString(i)+"_GPR_VAL <= sig_QUEUE_SLOT_"+toString(i)+"_VAL and sig_BYPASS_WRITE_"+toString(i)+"_WRITE_RD;"); 105 vhdl->set_body (0,"sig_BYPASS_WRITE_"+toString(i)+"_SPR_VAL <= sig_QUEUE_SLOT_"+toString(i)+"_VAL and sig_BYPASS_WRITE_"+toString(i)+"_WRITE_RE;"); 106 } 107 108 vhdl->set_body (0,""); 109 110 111 vhdl->set_comment(0,""); 112 vhdl->set_comment(0,"-----------------------------------"); 113 vhdl->set_comment(0,"-- Input Buffer "); 114 vhdl->set_comment(0,"-----------------------------------"); 115 vhdl->set_comment(0,""); 116 117 { 118 uint32_t min = 0; 119 uint32_t max, size; 120 121 if(_param->_have_port_context_id ) 122 { 123 size = _param->_size_context_id; 124 max = min-1+size; 125 vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_CONTEXT_ID;"); 126 min = max+1; 127 } 128 if(_param->_have_port_front_end_id ) 129 { 130 size = _param->_size_front_end_id; 131 max = min-1+size; 132 vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_FRONT_END_ID;"); 133 min = max+1; 134 } 135 if(_param->_have_port_ooo_engine_id ) 136 { 137 size = _param->_size_ooo_engine_id; 138 max = min-1+size; 139 vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_OOO_ENGINE_ID;"); 140 min = max+1; 141 } 142 if(_param->_have_port_rob_ptr) 143 { 144 size = _param->_size_rob_ptr; 145 max = min-1+size; 146 vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_PACKET_ID;"); 147 min = max+1; 148 } 149 150 size = 1; 151 max = min-1+size; 152 vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_WRITE_RD;"); 153 min = max+1; 154 155 size = _param->_size_general_register; 156 max = min-1+size; 157 vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_NUM_REG_RD;"); 158 min = max+1; 159 160 size = _param->_size_general_data; 161 max = min-1+size; 162 vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_DATA_RD;"); 163 min = max+1; 164 165 size = 1; 166 max = min-1+size; 167 vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_WRITE_RE;"); 168 min = max+1; 169 170 size = _param->_size_special_register; 171 max = min-1+size; 172 vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_NUM_REG_RE;"); 173 min = max+1; 174 175 size = _param->_size_special_data; 176 max = min-1+size; 177 vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_DATA_RE;"); 178 min = max+1; 179 180 size = _param->_size_exception; 181 max = min-1+size; 182 vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_EXCEPTION;"); 183 min = max+1; 184 185 size = 1; 186 max = min-1+size; 187 vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_NO_SEQUENCE;"); 188 min = max+1; 189 190 size = _param->_size_instruction_address; 191 max = min-1+size; 192 vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_ADDRESS;"); 193 min = max+1; 194 } 195 196 vhdl->set_body (0,""); 197 198 199 vhdl->set_comment(0,""); 200 vhdl->set_comment(0,"-----------------------------------"); 201 vhdl->set_comment(0,"-- Output Buffer "); 202 vhdl->set_comment(0,"-----------------------------------"); 203 vhdl->set_comment(0,""); 204 vhdl->set_body (0,"out_WRITE_QUEUE_OUT_VAL <= sig_WRITE_QUEUE_OUT_VAL;"); 205 if(_param->_have_port_context_id) 206 vhdl->set_body (0,"out_WRITE_QUEUE_OUT_CONTEXT_ID <= sig_WRITE_QUEUE_OUT_CONTEXT_ID ;"); 207 if(_param->_have_port_front_end_id) 208 vhdl->set_body (0,"out_WRITE_QUEUE_OUT_FRONT_END_ID <= sig_WRITE_QUEUE_OUT_FRONT_END_ID ;"); 209 if(_param->_have_port_ooo_engine_id) 210 vhdl->set_body (0,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID <= sig_WRITE_QUEUE_OUT_OOO_ENGINE_ID;"); 211 if(_param->_have_port_rob_ptr) 212 vhdl->set_body (0,"out_WRITE_QUEUE_OUT_PACKET_ID <= sig_WRITE_QUEUE_OUT_PACKET_ID ;"); 213 vhdl->set_body (0,"out_WRITE_QUEUE_OUT_FLAGS <= sig_WRITE_QUEUE_OUT_FLAGS ;"); 214 vhdl->set_body (0,"out_WRITE_QUEUE_OUT_EXCEPTION <= sig_WRITE_QUEUE_OUT_EXCEPTION ;"); 215 vhdl->set_body (0,"out_WRITE_QUEUE_OUT_NO_SEQUENCE <= sig_WRITE_QUEUE_OUT_NO_SEQUENCE ;"); 216 vhdl->set_body (0,"out_WRITE_QUEUE_OUT_ADDRESS <= sig_WRITE_QUEUE_OUT_ADDRESS ;"); 217 vhdl->set_body (0,"out_WRITE_QUEUE_OUT_DATA <= sig_WRITE_QUEUE_OUT_DATA ;"); 218 vhdl->set_body (""); 219 220 vhdl->set_body (0,"out_GPR_WRITE_0_VAL <= sig_GPR_WRITE_0_VAL;"); 221 if(_param->_have_port_ooo_engine_id) 222 vhdl->set_body (0,"out_GPR_WRITE_0_OOO_ENGINE_ID <= sig_GPR_WRITE_0_OOO_ENGINE_ID;"); 223 vhdl->set_body (0,"out_GPR_WRITE_0_NUM_REG <= sig_GPR_WRITE_0_NUM_REG;"); 224 vhdl->set_body (0,"out_GPR_WRITE_0_DATA <= sig_GPR_WRITE_0_DATA;"); 225 226 for (uint32_t i=1; i<_param->_nb_gpr_write; i++) 227 vhdl->set_body (0,"out_GPR_WRITE_"+toString(i)+"_VAL <= '0';"); 228 229 vhdl->set_body (0,"out_SPR_WRITE_0_VAL <= sig_SPR_WRITE_0_VAL;"); 230 if(_param->_have_port_ooo_engine_id) 231 vhdl->set_body (0,"out_SPR_WRITE_0_OOO_ENGINE_ID <= sig_SPR_WRITE_0_OOO_ENGINE_ID;"); 232 vhdl->set_body (0,"out_SPR_WRITE_0_NUM_REG <= sig_SPR_WRITE_0_NUM_REG;"); 233 vhdl->set_body (0,"out_SPR_WRITE_0_DATA <= sig_SPR_WRITE_0_DATA;"); 234 235 for (uint32_t i=1; i<_param->_nb_spr_write; i++) 236 vhdl->set_body (0,"out_SPR_WRITE_"+toString(i)+"_VAL <= '0';"); 237 238 vhdl->set_body (""); 239 240 for (uint32_t i=0; i<_param->_nb_bypass_write; i++) 241 { 242 vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL <= sig_BYPASS_WRITE_"+toString(i)+"_GPR_VAL;"); 243 vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG <= sig_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG;"); 244 vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA <= sig_BYPASS_WRITE_"+toString(i)+"_GPR_DATA;"); 245 246 vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL <= sig_BYPASS_WRITE_"+toString(i)+"_SPR_VAL;"); 247 vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG <= sig_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG;"); 248 vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA <= sig_BYPASS_WRITE_"+toString(i)+"_SPR_DATA;"); 249 250 if(_param->_have_port_ooo_engine_id) 251 vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID <= sig_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID;"); 252 } 253 27 254 log_printf(FUNC,Write_queue,FUNCTION,"End"); 28 255 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_vhdl_declaration.cpp
r81 r103 1 #ifdef VHDL1 #ifdef VHDL 2 2 /* 3 3 * $Id$ … … 24 24 { 25 25 log_printf(FUNC,Write_queue,FUNCTION,"Begin"); 26 27 vhdl->set_alias ("sig_QUEUE_INSERT_VAL ",1," in_WRITE_QUEUE_IN_VAL",std_logic_range(1)); 28 vhdl->set_alias ("sig_QUEUE_INSERT_ACK ",1,"out_WRITE_QUEUE_IN_ACK",std_logic_range(1)); 29 vhdl->set_signal ("sig_QUEUE_INSERT_DATA ",_param->_size_internal_queue); 30 vhdl->set_signal ("sig_QUEUE_RETIRE_DATA ",_param->_size_internal_queue); 31 vhdl->set_signal ("sig_QUEUE_RETIRE_VAL ",1); 32 vhdl->set_signal ("sig_QUEUE_RETIRE_ACK ",1); 33 for (uint32_t i=0; i<_param->_nb_bypass_write; i++) 34 { 35 vhdl->set_signal ("sig_QUEUE_SLOT_"+toString(i)+"_VAL",1); 36 vhdl->set_signal ("sig_QUEUE_SLOT_"+toString(i)+"_DATA",_param->_size_internal_queue); 37 } 38 for (uint32_t i=0; i<_param->_nb_bypass_write; i++) 39 { 40 vhdl->set_signal ("sig_BYPASS_WRITE_"+toString(i)+"_GPR_VAL",1); 41 vhdl->set_signal ("sig_BYPASS_WRITE_"+toString(i)+"_SPR_VAL",1); 42 } 43 44 vhdl->set_signal ("sig_GPR_WRITE_0_VAL",1); 45 vhdl->set_signal ("sig_SPR_WRITE_0_VAL",1); 46 vhdl->set_signal ("sig_DELETE_QUEUE_FRONT",1); 47 vhdl->set_signal ("sig_WRITE_QUEUE_OUT_VAL",1); 48 vhdl->set_signal ("reg_GPR_WRITE",1); 49 vhdl->set_signal ("reg_SPR_WRITE",1); 50 vhdl->set_signal ("sig_GPR_WRITE",1); 51 vhdl->set_signal ("sig_SPR_WRITE",1); 52 vhdl->set_signal ("reg_UPDATE",1); 53 54 uint32_t min = 0; 55 uint32_t max, size; 56 uint32_t min_ooo, max_ooo; 57 uint32_t pos_write_rd, min_gpr_num_reg, max_gpr_num_reg, min_gpr_data, max_gpr_data; 58 uint32_t pos_write_re, min_spr_num_reg, max_spr_num_reg, min_spr_data, max_spr_data; 59 60 if(_param->_have_port_context_id ) 61 { 62 size = _param->_size_context_id; 63 max = min-1+size; 64 vhdl->set_alias ("sig_WRITE_QUEUE_OUT_CONTEXT_ID ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 65 min = max+1; 66 } 67 if(_param->_have_port_front_end_id ) 68 { 69 size = _param->_size_front_end_id; 70 max = min-1+size; 71 vhdl->set_alias ("sig_WRITE_QUEUE_OUT_FRONT_END_ID ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 72 min = max+1; 73 } 74 if(_param->_have_port_ooo_engine_id ) 75 { 76 size = _param->_size_ooo_engine_id; 77 max = min-1+size; 78 vhdl->set_alias ("sig_WRITE_QUEUE_OUT_OOO_ENGINE_ID ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 79 vhdl->set_alias ("sig_GPR_WRITE_0_OOO_ENGINE_ID ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 80 vhdl->set_alias ("sig_SPR_WRITE_0_OOO_ENGINE_ID ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 81 min_ooo = min; 82 max_ooo = max; 83 min = max+1; 84 } 85 if(_param->_have_port_rob_ptr) 86 { 87 size = _param->_size_rob_ptr; 88 max = min-1+size; 89 vhdl->set_alias ("sig_WRITE_QUEUE_OUT_PACKET_ID ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 90 min = max+1; 91 } 92 93 size = 1; 94 max = min-1+size; 95 vhdl->set_alias ("sig_WRITE_RD ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 96 pos_write_rd = max; 97 min = max+1; 98 99 size = _param->_size_general_register; 100 max = min-1+size; 101 vhdl->set_alias ("sig_GPR_WRITE_0_NUM_REG ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 102 min_gpr_num_reg = min; 103 max_gpr_num_reg = max; 104 min = max+1; 105 106 size = _param->_size_general_data; 107 max = min-1+size; 108 vhdl->set_alias ("sig_GPR_WRITE_0_DATA ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 109 vhdl->set_alias ("sig_WRITE_QUEUE_OUT_DATA ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 110 min_gpr_data = min; 111 max_gpr_data = max; 112 min = max+1; 113 114 size = 1; 115 max = min-1+size; 116 vhdl->set_alias ("sig_WRITE_RE ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 117 pos_write_re = max; 118 min = max+1; 119 120 size = _param->_size_special_register; 121 max = min-1+size; 122 vhdl->set_alias ("sig_SPR_WRITE_0_NUM_REG ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 123 min_spr_num_reg = min; 124 max_spr_num_reg = max; 125 min = max+1; 126 127 size = _param->_size_special_data; 128 max = min-1+size; 129 vhdl->set_alias ("sig_SPR_WRITE_0_DATA ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 130 vhdl->set_alias ("sig_WRITE_QUEUE_OUT_FLAGS ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 131 min_spr_data = min; 132 max_spr_data = max; 133 min = max+1; 134 135 size = _param->_size_exception; 136 max = min-1+size; 137 vhdl->set_alias ("sig_WRITE_QUEUE_OUT_EXCEPTION ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 138 min = max+1; 139 140 size = 1; 141 max = min-1+size; 142 vhdl->set_alias ("sig_WRITE_QUEUE_OUT_NO_SEQUENCE ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 143 min = max+1; 144 145 size = _param->_size_instruction_address; 146 max = min-1+size; 147 vhdl->set_alias ("sig_WRITE_QUEUE_OUT_ADDRESS ",std_logic(size),"sig_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 148 min = max+1; 149 150 for (uint32_t i=0; i<_param->_nb_bypass_write; i++) 151 { 152 if(_param->_have_port_ooo_engine_id) 153 vhdl->set_alias ("sig_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID",std_logic(_param->_size_ooo_engine_id),"sig_QUEUE_SLOT_"+toString(i)+"_DATA",std_logic_range(_param->_size_internal_queue,max_ooo,min_ooo)); 154 vhdl->set_alias ("sig_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG",std_logic(_param->_size_general_register),"sig_QUEUE_SLOT_"+toString(i)+"_DATA",std_logic_range(_param->_size_internal_queue,max_gpr_num_reg,min_gpr_num_reg)); 155 vhdl->set_alias ("sig_BYPASS_WRITE_"+toString(i)+"_GPR_DATA",std_logic(_param->_size_general_data),"sig_QUEUE_SLOT_"+toString(i)+"_DATA",std_logic_range(_param->_size_internal_queue,max_gpr_data,min_gpr_data)); 156 vhdl->set_alias ("sig_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG",std_logic(_param->_size_special_register),"sig_QUEUE_SLOT_"+toString(i)+"_DATA",std_logic_range(_param->_size_internal_queue,max_spr_num_reg,min_spr_num_reg)); 157 vhdl->set_alias ("sig_BYPASS_WRITE_"+toString(i)+"_SPR_DATA",std_logic(_param->_size_special_data),"sig_QUEUE_SLOT_"+toString(i)+"_DATA",std_logic_range(_param->_size_internal_queue,max_spr_data,min_spr_data)); 158 159 vhdl->set_alias ("sig_BYPASS_WRITE_"+toString(i)+"_WRITE_RD",std_logic(1),"sig_QUEUE_SLOT_"+toString(i)+"_DATA",std_logic_range(_param->_size_internal_queue,pos_write_rd,pos_write_rd)); 160 vhdl->set_alias ("sig_BYPASS_WRITE_"+toString(i)+"_WRITE_RE",std_logic(1),"sig_QUEUE_SLOT_"+toString(i)+"_DATA",std_logic_range(_param->_size_internal_queue,pos_write_re,pos_write_re)); 161 } 162 26 163 log_printf(FUNC,Write_queue,FUNCTION,"End"); 27 164 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Queue.h
r101 r103 75 75 76 76 // ~~~~~[ Interface "slot" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 77 public : SC_OUT(Tcontrol_t) ** out_SLOT_VAL ; 78 public : SC_OUT(Tdata_t ) ** out_SLOT_DATA; 77 public : SC_OUT(Tcontrol_t) ** out_SLOT_VAL ; //[nb_port_slot] 78 public : SC_OUT(Tdata_t ) ** out_SLOT_DATA; //[nb_port_slot] 79 79 80 80 // ~~~~~[ Interface "ptr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_vhdl_body.cpp
r101 r103 46 46 else 47 47 vhdl->set_body (0,"signal_SLOT_"+toString(i)+" <= const_PTR_INIT when signal_SLOT_"+toString(i-1)+" = const_PTR_MAX else signal_SLOT_"+toString(i-1)+"+'1';"); 48 48 49 } 49 50 … … 51 52 { 52 53 if (_param->_nb_port_slot > 1) 53 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_VAL <= '1' when reg_NB_ELT > "+std_logic_cst(log2(_param->_size_queue+1),i)+" else '0';"); 54 else 55 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_VAL <= not signal_EMPTY;"); 56 54 vhdl->set_body (0,"signal_SLOT_"+toString(i)+"_VAL <= '1' when reg_NB_ELT > "+std_logic_cst(log2(_param->_size_queue+1),i)+" else '0';"); 55 else 56 vhdl->set_body (0,"signal_SLOT_"+toString(i)+"_VAL <= not signal_EMPTY;"); 57 58 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_VAL <= signal_SLOT_"+toString(i)+"_VAL;"); 59 60 #ifdef SYSTEMC_VHDL_COMPATIBILITY 61 std::string str_val_disable=std_logic_cst(_param->_size_data,0)+" when signal_SLOT_"+toString(i)+"_VAL='0' else"; 62 #endif 57 63 if (_param->_nb_port_slot > 1) 58 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <= reg_DATA(conv_integer(signal_SLOT_"+toString(i)+"));"); 64 { 65 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <= "); 66 #ifdef SYSTEMC_VHDL_COMPATIBILITY 67 vhdl->set_body (1,str_val_disable); 68 #endif 69 vhdl->set_body (1,"reg_DATA(conv_integer(signal_SLOT_"+toString(i)+"));"); 70 } 59 71 else 60 72 if (_param->_size_queue > 1) 61 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <= reg_DATA(conv_integer(signal_PTR_READ));"); 73 { 74 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <="); 75 #ifdef SYSTEMC_VHDL_COMPATIBILITY 76 vhdl->set_body (1,str_val_disable); 77 #endif 78 vhdl->set_body (1,"reg_DATA(conv_integer(signal_PTR_READ));"); 79 } 62 80 else 63 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <= reg_DATA(conv_integer(0));"); 81 { 82 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <="); 83 #ifdef SYSTEMC_VHDL_COMPATIBILITY 84 vhdl->set_body (1,str_val_disable); 85 #endif 86 vhdl->set_body (1,"reg_DATA(conv_integer(0));"); 87 } 64 88 } 65 89 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_vhdl_declaration.cpp
r100 r103 38 38 } 39 39 40 if (_param->_nb_port_slot>0) 41 for (uint32_t i=0; i<_param->_nb_port_slot; ++i) 42 vhdl->set_signal ("signal_SLOT_"+toString(i)+"_VAL", 1); 43 40 44 if (_param->_nb_port_slot>1) 41 45 { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common
r97 r103 23 23 24 24 #-----[ Directory ]---------------------------------------- 25 #DIR_TMP = . 25 26 DIR_TMP = $(MORPHEO_TMP) 26 27 DIR_INC = include -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis
r96 r103 29 29 declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ 30 30 if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; \ 31 declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl|$(GREP_NOT) "(_Pack\.|_Testbench\.)")); \ 32 declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ 33 if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; \ 31 34 declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \ 32 35 declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ 33 if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; \34 declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl|$(GREP_NOT) "(_Pack\.|_Testbench\.)")); \35 declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \36 36 if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; 37 37 38 38 39 sim : vhdl … … 85 86 @\ 86 87 if $(TEST) -f Makefile.mkf; then $(MAKE) -f Makefile.mkf clean; fi; \ 87 $(RM) $(DIR_WORK) transcript Makefile.mkf $(FPGA_CFG_FILE_LOCAL)*.wlf;88 $(RM) $(DIR_WORK) transcript Makefile.mkf *.wlf; 88 89 89 90 synthesis_clean_all : synthesis_clean -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf
r100 r103 3 3 # 4 4 5 all: _Generic/Queue/SelfTest _Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest 5 all: _Generic/Queue/SelfTest _Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest _Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest 6 6 7 7 _Generic/Queue/SelfTest: … … 11 11 gmake all -C Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest 12 12 13 _Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest: 14 gmake all -C Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest 15 13 16 clean: 14 17 gmake clean -C Generic/Queue/SelfTest 15 18 gmake clean -C Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest 19 gmake clean -C Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest 16 20 17 21 re: clean all … … 20 24 gmake install -C Generic/Queue/SelfTest 21 25 gmake install -C Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest 26 gmake install -C Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest 22 27 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h
r102 r103 10 10 #define MORPHEO_MAJOR_VERSION 0 11 11 #define MORPHEO_MINOR_VERSION 2 12 #define MORPHEO_REVISION "10 2"12 #define MORPHEO_REVISION "103" 13 13 #define MORPHEO_CODENAME "Castor" 14 14 15 #define MORPHEO_DATE_DAY "1 5"15 #define MORPHEO_DATE_DAY "16" 16 16 #define MORPHEO_DATE_MONTH "01" 17 17 #define MORPHEO_DATE_YEAR "2009" -
trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info
r100 r103 24 24 #target_dep all Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest 25 25 target_dep all Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest 26 target_dep all Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest 27 target_dep all Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest 28 29 26 30 # mkf include path 27 31 var_define _mkf_path include_mkf -
trunk/IPs/systemC/processor/Morpheo/Common/include/ToBase2.h
r88 r103 17 17 std::ostringstream res; 18 18 T mask = 1<<(size-1); 19 20 while (mask != 0)19 20 for (uint32_t i=0; i<size; ++i) 21 21 { 22 22 res << ((value&mask)?'1':'0');
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