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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 15 years ago
Almost complete design with Test and test platform
Property svn:keywords set to `Id`
File size: 48.4 KB

Line
1	/*
2	* $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/include/test.h"
10	#include "Behavioural/include/Allocation.h"
11
12	void test (string name,
13	morpheo::behavioural::core::multi_front_end::front_end::context_state::Parameters * _param)
14	{
15	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
16
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
19	#endif
20
21	Tusage_t _usage = USE_ALL;
22
23	// _usage = usage_unset(_usage,USE_SYSTEMC );
24	// _usage = usage_unset(_usage,USE_VHDL );
25	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
26	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
27	// _usage = usage_unset(_usage,USE_POSITION );
28	// _usage = usage_unset(_usage,USE_STATISTICS );
29	// _usage = usage_unset(_usage,USE_INFORMATION );
30
31	Context_State * _Context_State = new Context_State
32	(name.c_str(),
33	#ifdef STATISTICS
34	_parameters_statistics,
35	#endif
36	_param,
37	_usage);
38
39	#ifdef SYSTEMC
40	if (usage_is_set(_usage,USE_SYSTEMC))
41	{
42	/*********************************************************************
43	* Déclarations des signaux
44	*********************************************************************/
45	string rename;
46
47	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
48	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
49
50	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_VAL ," in_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
51	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,"out_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
52	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
53	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
54	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ," in_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context);
55	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ," in_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
56	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ," in_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
57
58	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_VAL ," in_DECOD_EVENT_VAL ",Tcontrol_t ,_param->_nb_decod_unit);
59	ALLOC1_SC_SIGNAL(out_DECOD_EVENT_ACK ,"out_DECOD_EVENT_ACK ",Tcontrol_t ,_param->_nb_decod_unit);
60	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ," in_DECOD_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_decod_unit);
61	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ," in_DECOD_EVENT_DEPTH ",Tdepth_t ,_param->_nb_decod_unit);
62	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_TYPE ," in_DECOD_EVENT_TYPE ",Tevent_type_t,_param->_nb_decod_unit);
63	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ," in_DECOD_EVENT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_decod_unit);
64	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ," in_DECOD_EVENT_ADDRESS ",Taddress_t ,_param->_nb_decod_unit);
65	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ," in_DECOD_EVENT_ADDRESS_EPCR ",Taddress_t ,_param->_nb_decod_unit);
66
67	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t );
68	ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t );
69	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t );
70	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t );
71	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t);
72	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
73	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t );
74	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t );
75	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t );
76	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Taddress_t );
77
78	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
79	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
80	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
81	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
82	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
83	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ," in_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
84	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ," in_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
85	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ," in_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
86
87
88	ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context );
89	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context );
90	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context );
91
92	ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context );
93	ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context );
94	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS ,"out_EVENT_ADDRESS ",Taddress_t ,_param->_nb_context );
95	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,"out_EVENT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_context );
96	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context );
97	ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context );
98
99	ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context );
100	ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context );
101	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EPCR ,"out_SPR_EVENT_EPCR ",Taddress_t ,_param->_nb_context );
102	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR ,"out_SPR_EVENT_EEAR ",Taddress_t ,_param->_nb_context );
103	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,"out_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_context );
104	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,"out_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_context );
105	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,"out_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context );
106
107	ALLOC1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,"out_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context );
108
109	ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context );
110
111	ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context );
112	ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context );
113
114	ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_context );
115
116	/********************************************************
117	* Instanciation
118	********************************************************/
119
120	msg(_("<%s> : Instanciation of _Context_State.\n"),name.c_str());
121
122	((_Context_State->in_CLOCK)) ((in_CLOCK));
123	((_Context_State->in_NRESET)) ((in_NRESET));
124
125	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_VAL ,_param->_nb_context);
126	INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_EVENT_ACK ,_param->_nb_context);
127	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
128	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
129	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
130	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
131	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
132	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
133	INSTANCE1_SC_SIGNAL(_Context_State,out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
134	if (_param->_have_port_context_id)
135	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
136	if (_param->_have_port_depth)
137	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
138	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
139	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
140	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
141	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
142
143	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_VAL );
144	INSTANCE_SC_SIGNAL (_Context_State,out_COMMIT_EVENT_ACK );
145	if (_param->_have_port_context_id)
146	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_CONTEXT_ID );
147	if (_param->_have_port_depth)
148	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_DEPTH );
149	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_TYPE );
150	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT );
151	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS );
152	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR );
153	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
154	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR );
155
156	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
157	INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
158	if (_param->_have_port_context_id)
159	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
160	if (_param->_have_port_depth)
161	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
162	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
163	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
164	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
165	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
166
167	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_DECOD_ALL ,_param->_nb_context );
168	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_ALL ,_param->_nb_context );
169	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_MEM ,_param->_nb_context );
170
171	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_VAL ,_param->_nb_context );
172	INSTANCE1_SC_SIGNAL(_Context_State, in_EVENT_ACK ,_param->_nb_context );
173	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS ,_param->_nb_context );
174	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
175	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
176	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_IS_DS_TAKE ,_param->_nb_context );
177
178	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_VAL ,_param->_nb_context );
179	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_EVENT_ACK ,_param->_nb_context );
180	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EPCR ,_param->_nb_context );
181	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR ,_param->_nb_context );
182	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR_WEN ,_param->_nb_context );
183	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_DSX ,_param->_nb_context );
184	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context );
185
186	INSTANCE1_SC_SIGNAL(_Context_State,out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
187
188	for (uint32_t i=0; i<_param->_nb_context; i++)
189	if (_param->_have_port_depth)
190	INSTANCE_SC_SIGNAL(_Context_State, in_DEPTH_MIN [i]);
191
192	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_IEE ,_param->_nb_context );
193	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_EPH ,_param->_nb_context );
194
195	INSTANCE1_SC_SIGNAL(_Context_State, in_INTERRUPT_ENABLE ,_param->_nb_context );
196
197	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
198
199	Time * _time = new Time();
200
201	/********************************************************
202	* Simulation - Begin
203	********************************************************/
204
205	// Initialisation
206
207	const uint32_t seed = 0;
208	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
209
210	srand(seed);
211
212	const int32_t percent_transaction_decod_event = 75;
213	const int32_t percent_transaction_commit_event = 75;
214	const int32_t percent_transaction_branch_complete = 75;
215	const int32_t percent_transaction_event = 75;
216	const int32_t percent_transaction_spr = 75;
217
218	SC_START(0);
219	LABEL("Initialisation");
220
221	LABEL("Reset");
222	in_NRESET->write(0);
223	SC_START(5);
224	in_NRESET->write(1);
225
226	LABEL("Loop of Test");
227
228	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
229	{
230	LABEL("Iteration %d",iteration);
231	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
232	in_DECOD_EVENT_VAL [i]->write(0);
233	in_COMMIT_EVENT_VAL ->write(0);
234	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
235	in_BRANCH_COMPLETE_VAL [i]->write(0);
236
237	for (uint32_t i=0; i<_param->_nb_context; i++)
238	{
239	in_BRANCH_EVENT_VAL [i]->write(0);
240	in_EVENT_ACK [i]->write(0);
241	in_SPR_EVENT_ACK [i]->write(0);
242	in_SPR_SR_IEE [i]->write(0);
243	in_SPR_SR_EPH [i]->write(0);
244	in_INTERRUPT_ENABLE [i]->write(0);
245
246	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[i]->read(), 1);
247	}
248
249	for (uint32_t i=0; i<_param->_nb_context; i++)
250	if (_param->_have_port_depth)
251	in_DEPTH_MIN [i]->write((_param->_array_size_depth[i]==0)?0:(i%_param->_array_size_depth[i]));
252
253	uint32_t context = rand()%_param->_nb_context;
254
255	if (1)
256	{
257	SC_START(3);
258
259	LABEL("msync (begin)");
260	in_NB_INST_DECOD_ALL [context]->write(1);
261	in_NB_INST_COMMIT_ALL [context]->write(1);
262	in_NB_INST_COMMIT_MEM [context]->write(1);
263
264	uint32_t port = rand()%_param->_nb_decod_unit;
265
266	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
267	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
268	in_DECOD_EVENT_ADDRESS [port]->write(0x100);
269	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef);
270	if (_param->_have_port_depth)
271	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
272	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_MSYNC);
273
274	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
275
276	do
277	{
278	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
279
280	SC_START(1);
281	}
282	while (not ( in_DECOD_EVENT_VAL [port]->read() and
283	out_DECOD_EVENT_ACK [port]->read()));
284	in_DECOD_EVENT_VAL [port]->write(0);
285
286	LABEL("msync (wait end)");
287	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
288
289	SC_START(3);
290
291	in_NB_INST_DECOD_ALL [context]->write(0);
292	in_NB_INST_COMMIT_ALL [context]->write(1);
293	in_NB_INST_COMMIT_MEM [context]->write(0);
294
295	SC_START(1);
296
297	LABEL("msync (send decod)");
298	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
299
300	SC_START(3);
301
302	in_NB_INST_DECOD_ALL [context]->write(1);
303	SC_START(1);
304
305	LABEL("msync (wait end)");
306	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
307	in_NB_INST_DECOD_ALL [context]->write(0);
308	in_NB_INST_COMMIT_MEM [context]->write(1);
309
310	SC_START(3);
311
312	in_NB_INST_COMMIT_MEM [context]->write(0);
313	SC_START(1);
314	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
315	}
316
317	if (1)
318	{
319	SC_START(3);
320
321	LABEL("psync (begin)");
322	in_NB_INST_DECOD_ALL [context]->write(1);
323	in_NB_INST_COMMIT_ALL [context]->write(1);
324	in_NB_INST_COMMIT_MEM [context]->write(1);
325
326	uint32_t port = rand()%_param->_nb_decod_unit;
327
328	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
329	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
330	in_DECOD_EVENT_ADDRESS [port]->write(0x200);
331	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe);
332	if (_param->_have_port_depth)
333	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
334	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC);
335
336	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
337
338	do
339	{
340	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
341
342	SC_START(1);
343	}
344	while (not ( in_DECOD_EVENT_VAL [port]->read() and
345	out_DECOD_EVENT_ACK [port]->read()));
346	in_DECOD_EVENT_VAL [port]->write(0);
347
348	LABEL("psync (wait end)");
349	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
350
351	SC_START(3);
352
353	in_NB_INST_DECOD_ALL [context]->write(0);
354	in_NB_INST_COMMIT_ALL [context]->write(0);
355	in_NB_INST_COMMIT_MEM [context]->write(0);
356
357	SC_START(1);
358
359	bool find = false;
360	do
361	{
362	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
363
364	SC_START(0);
365
366	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
367	{
368	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201);
369	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe);
370	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
371	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
372
373	find = true;
374	}
375
376	SC_START(1);
377	}
378	while (not find);
379
380	in_EVENT_ACK [context]->write(0);
381	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
382	}
383
384	if (1)
385	{
386	SC_START(3);
387
388	LABEL("csync (begin)");
389	in_NB_INST_DECOD_ALL [context]->write(1);
390	in_NB_INST_COMMIT_ALL [context]->write(1);
391	in_NB_INST_COMMIT_MEM [context]->write(1);
392
393	uint32_t port = rand()%_param->_nb_decod_unit;
394
395	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
396	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
397	in_DECOD_EVENT_ADDRESS [port]->write(0x200);
398	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe);
399	if (_param->_have_port_depth)
400	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
401	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC);
402
403	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
404
405	do
406	{
407	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
408
409	SC_START(1);
410	}
411	while (not ( in_DECOD_EVENT_VAL [port]->read() and
412	out_DECOD_EVENT_ACK [port]->read()));
413	in_DECOD_EVENT_VAL [port]->write(0);
414
415	LABEL("csync (wait end)");
416	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
417
418	SC_START(3);
419
420	in_NB_INST_DECOD_ALL [context]->write(0);
421	in_NB_INST_COMMIT_ALL [context]->write(0);
422	in_NB_INST_COMMIT_MEM [context]->write(0);
423
424	SC_START(1);
425
426	bool find = false;
427	do
428	{
429	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
430
431	SC_START(0);
432
433	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
434	{
435	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201);
436	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe);
437	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
438	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
439
440	find = true;
441	}
442
443	SC_START(1);
444	}
445	while (not find);
446	in_EVENT_ACK [context]->write(0);
447	}
448
449	if (1)
450	{
451	SC_START(3);
452
453	LABEL("spr (begin)");
454	in_NB_INST_DECOD_ALL [context]->write(1);
455	in_NB_INST_COMMIT_ALL [context]->write(1);
456	in_NB_INST_COMMIT_MEM [context]->write(1);
457
458	uint32_t port = rand()%_param->_nb_decod_unit;
459
460	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
461	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
462	in_DECOD_EVENT_ADDRESS [port]->write(0x100);
463	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef);
464	if (_param->_have_port_depth)
465	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
466	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_SPR_ACCESS);
467
468	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
469
470	do
471	{
472	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
473
474	SC_START(1);
475	}
476	while (not ( in_DECOD_EVENT_VAL [port]->read() and
477	out_DECOD_EVENT_ACK [port]->read()));
478	in_DECOD_EVENT_VAL [port]->write(0);
479
480	LABEL("spr (wait end)");
481	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
482
483	SC_START(3);
484
485	in_NB_INST_DECOD_ALL [context]->write(0);
486	in_NB_INST_COMMIT_ALL [context]->write(0);
487	in_NB_INST_COMMIT_MEM [context]->write(0);
488
489	SC_START(1);
490
491	LABEL("spr (send decod)");
492	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
493
494	SC_START(3);
495
496	in_NB_INST_DECOD_ALL [context]->write(1);
497	SC_START(1);
498
499	LABEL("spr (wait end)");
500	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
501	in_NB_INST_DECOD_ALL [context]->write(0);
502	in_NB_INST_COMMIT_ALL [context]->write(1);
503
504	SC_START(3);
505
506	in_NB_INST_COMMIT_ALL [context]->write(0);
507	SC_START(1);
508	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
509	}
510
511	if (1)
512	{
513	SC_START(3);
514
515	LABEL("miss (begin)");
516	in_NB_INST_DECOD_ALL [context]->write(1);
517	in_NB_INST_COMMIT_ALL [context]->write(1);
518	in_NB_INST_COMMIT_MEM [context]->write(1);
519
520	uint32_t port = rand()%_param->_nb_inst_branch_complete;
521
522	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
523	if (_param->_have_port_depth)
524	in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
525	in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400);
526	in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500);
527	in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
528	in_BRANCH_COMPLETE_TAKE [port]->write(0);
529
530	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
531
532	do
533	{
534	in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
535
536	SC_START(1);
537	}
538	while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
539	out_BRANCH_COMPLETE_ACK [port]->read()));
540	in_BRANCH_COMPLETE_VAL [port]->write(0);
541
542	LABEL("miss (wait end)");
543	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
544
545	SC_START(3);
546
547	in_NB_INST_DECOD_ALL [context]->write(0);
548	in_NB_INST_COMMIT_ALL [context]->write(0);
549	in_NB_INST_COMMIT_MEM [context]->write(0);
550
551	SC_START(1);
552
553	LABEL("miss (wait event)");
554
555
556	bool find = false;
557	do
558	{
559	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
560
561	SC_START(0);
562
563	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
564	{
565	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x401);
566	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x500);
567	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
568	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
569
570	find = true;
571	}
572
573	SC_START(1);
574	}
575	while (not find);
576
577	in_EVENT_ACK [context]->write(0);
578
579	}
580
581	if (1)
582	{
583	SC_START(3);
584
585	LABEL("miss (begin)");
586	in_NB_INST_DECOD_ALL [context]->write(1);
587	in_NB_INST_COMMIT_ALL [context]->write(1);
588	in_NB_INST_COMMIT_MEM [context]->write(1);
589
590	uint32_t port = rand()%_param->_nb_inst_branch_complete;
591
592	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
593	if (_param->_have_port_depth)
594	in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
595	in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600);
596	in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700);
597	in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
598	in_BRANCH_COMPLETE_TAKE [port]->write(1);
599
600	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
601
602	do
603	{
604	in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
605
606	SC_START(1);
607	}
608	while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
609	out_BRANCH_COMPLETE_ACK [port]->read()));
610	in_BRANCH_COMPLETE_VAL [port]->write(0);
611
612	LABEL("miss (wait end)");
613	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
614
615	SC_START(3);
616
617	in_NB_INST_DECOD_ALL [context]->write(0);
618	in_NB_INST_COMMIT_ALL [context]->write(0);
619	in_NB_INST_COMMIT_MEM [context]->write(0);
620
621	SC_START(1);
622
623	LABEL("miss (wait event)");
624
625	bool find = false;
626	do
627	{
628	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
629
630	SC_START(0);
631
632	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
633	{
634	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x601);
635	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x700);
636	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),1);
637	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),1);
638
639	find = true;
640	}
641
642	SC_START(1);
643	}
644	while (not find);
645
646	in_EVENT_ACK [context]->write(0);
647	}
648
649	if (1)
650	{
651	SC_START(3);
652
653	LABEL("exception (begin)");
654	in_NB_INST_DECOD_ALL [context]->write(1);
655	in_NB_INST_COMMIT_ALL [context]->write(1);
656	in_NB_INST_COMMIT_MEM [context]->write(1);
657
658	uint32_t port = rand()%_param->_nb_decod_unit;
659
660	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
661	if (_param->_have_port_depth)
662	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
663	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
664	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
665	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
666	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
667
668	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
669
670	do
671	{
672	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
673
674	SC_START(1);
675	}
676	while (not ( in_DECOD_EVENT_VAL [port]->read() and
677	out_DECOD_EVENT_ACK [port]->read()));
678	in_DECOD_EVENT_VAL [port]->write(0);
679
680	LABEL("exception (wait end)");
681	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
682
683	SC_START(3);
684
685	in_NB_INST_DECOD_ALL [context]->write(0);
686	in_NB_INST_COMMIT_ALL [context]->write(0);
687	in_NB_INST_COMMIT_MEM [context]->write(0);
688
689	SC_START(1);
690
691	LABEL("exception (wait event)");
692
693	bool find = false;
694	do
695	{
696	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
697
698	SC_START(0);
699
700	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
701	{
702	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
703	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
704	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
705	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
706
707	find = true;
708	}
709
710	SC_START(1);
711	}
712	while (not find);
713
714	in_EVENT_ACK [context]->write(0);
715
716	LABEL("exception (wait spr)");
717
718	find = false;
719	do
720	{
721	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
722
723	SC_START(0);
724
725	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
726	{
727	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900);
728	//TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),);
729	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
730	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
731	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
732
733	find = true;
734	}
735
736	SC_START(1);
737	}
738	while (not find);
739
740	in_SPR_EVENT_ACK [context]->write(0);
741	}
742
743	if (1)
744	{
745	SC_START(3);
746
747	LABEL("exception (begin)");
748	in_NB_INST_DECOD_ALL [context]->write(1);
749	in_NB_INST_COMMIT_ALL [context]->write(1);
750	in_NB_INST_COMMIT_MEM [context]->write(1);
751
752	uint32_t port = rand()%_param->_nb_decod_unit;
753
754	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
755	if (_param->_have_port_depth)
756	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
757	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
758	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(1);
759	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
760	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
761
762	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
763
764	do
765	{
766	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
767
768	SC_START(1);
769	}
770	while (not ( in_DECOD_EVENT_VAL [port]->read() and
771	out_DECOD_EVENT_ACK [port]->read()));
772	in_DECOD_EVENT_VAL [port]->write(0);
773
774	LABEL("exception (wait end)");
775	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
776
777	SC_START(3);
778
779	in_NB_INST_DECOD_ALL [context]->write(0);
780	in_NB_INST_COMMIT_ALL [context]->write(0);
781	in_NB_INST_COMMIT_MEM [context]->write(0);
782
783	SC_START(1);
784
785	LABEL("exception (wait event)");
786
787	bool find = false;
788	do
789	{
790	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
791
792	SC_START(0);
793
794	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
795	{
796	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
797	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
798	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
799	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
800
801	find = true;
802	}
803
804	SC_START(1);
805	}
806	while (not find);
807
808	in_EVENT_ACK [context]->write(0);
809
810	LABEL("exception (wait spr)");
811
812	find = false;
813	do
814	{
815	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
816
817	SC_START(0);
818
819	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
820	{
821	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900);
822	//TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),);
823	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
824	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
825	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
826
827	find = true;
828	}
829
830	SC_START(1);
831	}
832	while (not find);
833
834	in_SPR_EVENT_ACK [context]->write(0);
835	}
836
837	if (1)
838	{
839	SC_START(3);
840
841	LABEL("exception (begin)");
842	in_NB_INST_DECOD_ALL [context]->write(1);
843	in_NB_INST_COMMIT_ALL [context]->write(1);
844	in_NB_INST_COMMIT_MEM [context]->write(1);
845
846	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
847	if (_param->_have_port_depth)
848	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
849	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
850	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0);
851	in_COMMIT_EVENT_ADDRESS ->write(0xa00);
852	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00);
853	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00);
854	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
855
856	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
857
858	do
859	{
860	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
861
862	SC_START(1);
863	}
864	while (not ( in_COMMIT_EVENT_VAL ->read() and
865	out_COMMIT_EVENT_ACK ->read()));
866	in_COMMIT_EVENT_VAL ->write(0);
867
868	LABEL("exception (wait end)");
869	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
870
871	SC_START(3);
872
873	in_NB_INST_DECOD_ALL [context]->write(0);
874	in_NB_INST_COMMIT_ALL [context]->write(0);
875	in_NB_INST_COMMIT_MEM [context]->write(0);
876
877	SC_START(1);
878
879	LABEL("exception (wait event)");
880
881	bool find = false;
882	do
883	{
884	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
885
886	SC_START(0);
887
888	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
889	{
890	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
891	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
892	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
893	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
894
895	find = true;
896	}
897
898	SC_START(1);
899	}
900	while (not find);
901
902	in_EVENT_ACK [context]->write(0);
903
904	LABEL("exception (wait spr)");
905
906	find = false;
907	do
908	{
909	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
910
911	SC_START(0);
912
913	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
914	{
915	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00);
916	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00);
917	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
918	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
919	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
920
921	find = true;
922	}
923
924	SC_START(1);
925	}
926	while (not find);
927
928	in_SPR_EVENT_ACK [context]->write(0);
929	}
930
931	if (1)
932	{
933	SC_START(3);
934
935	LABEL("exception (begin)");
936	in_NB_INST_DECOD_ALL [context]->write(1);
937	in_NB_INST_COMMIT_ALL [context]->write(1);
938	in_NB_INST_COMMIT_MEM [context]->write(1);
939
940	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
941	if (_param->_have_port_depth)
942	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
943	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
944	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1);
945	in_COMMIT_EVENT_ADDRESS ->write(0xd00);
946	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00);
947	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00);
948	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
949
950	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
951
952	do
953	{
954	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
955
956	SC_START(1);
957	}
958	while (not ( in_COMMIT_EVENT_VAL ->read() and
959	out_COMMIT_EVENT_ACK ->read()));
960	in_COMMIT_EVENT_VAL ->write(0);
961
962	LABEL("exception (wait end)");
963	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
964
965	SC_START(3);
966
967	in_NB_INST_DECOD_ALL [context]->write(0);
968	in_NB_INST_COMMIT_ALL [context]->write(0);
969	in_NB_INST_COMMIT_MEM [context]->write(0);
970
971	SC_START(1);
972
973	LABEL("exception (wait event)");
974
975	bool find = false;
976	do
977	{
978	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
979
980	SC_START(0);
981
982	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
983	{
984	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
985	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
986	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
987	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
988
989	find = true;
990	}
991
992	SC_START(1);
993	}
994	while (not find);
995
996	in_EVENT_ACK [context]->write(0);
997
998	LABEL("exception (wait spr)");
999
1000	find = false;
1001	do
1002	{
1003	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1004
1005	SC_START(0);
1006
1007	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1008	{
1009	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00);
1010	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00);
1011	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
1012	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
1013	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1014
1015	find = true;
1016	}
1017
1018	SC_START(1);
1019	}
1020	while (not find);
1021
1022	in_SPR_EVENT_ACK [context]->write(0);
1023	}
1024
1025	if (1)
1026	{
1027	SC_START(3);
1028
1029	LABEL("exception (begin)");
1030	in_NB_INST_DECOD_ALL [context]->write(1);
1031	in_NB_INST_COMMIT_ALL [context]->write(1);
1032	in_NB_INST_COMMIT_MEM [context]->write(1);
1033
1034	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1035	if (_param->_have_port_depth)
1036	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
1037	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1038	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0);
1039	in_COMMIT_EVENT_ADDRESS ->write(0xa00);
1040	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00);
1041	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00);
1042	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
1043
1044	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1045
1046	do
1047	{
1048	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1049
1050	SC_START(1);
1051	}
1052	while (not ( in_COMMIT_EVENT_VAL ->read() and
1053	out_COMMIT_EVENT_ACK ->read()));
1054	in_COMMIT_EVENT_VAL ->write(0);
1055
1056	LABEL("exception (wait end)");
1057	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1058
1059	SC_START(3);
1060
1061	in_NB_INST_DECOD_ALL [context]->write(0);
1062	in_NB_INST_COMMIT_ALL [context]->write(0);
1063	in_NB_INST_COMMIT_MEM [context]->write(0);
1064
1065	SC_START(1);
1066
1067	LABEL("exception (wait event)");
1068
1069	bool find = false;
1070	do
1071	{
1072	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1073
1074	SC_START(0);
1075
1076	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1077	{
1078	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
1079	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
1080	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1081	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1082
1083	find = true;
1084	}
1085
1086	SC_START(1);
1087	}
1088	while (not find);
1089
1090	in_EVENT_ACK [context]->write(0);
1091
1092	LABEL("exception (wait spr)");
1093
1094	find = false;
1095	do
1096	{
1097	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1098
1099	SC_START(0);
1100
1101	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1102	{
1103	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00);
1104	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00);
1105	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1);
1106	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
1107	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1108
1109	find = true;
1110	}
1111
1112	SC_START(1);
1113	}
1114	while (not find);
1115
1116	in_SPR_EVENT_ACK [context]->write(0);
1117	}
1118
1119	if (1)
1120	{
1121	SC_START(3);
1122
1123	LABEL("exception (begin)");
1124	in_NB_INST_DECOD_ALL [context]->write(1);
1125	in_NB_INST_COMMIT_ALL [context]->write(1);
1126	in_NB_INST_COMMIT_MEM [context]->write(1);
1127
1128	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1129	if (_param->_have_port_depth)
1130	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
1131	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1132	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1);
1133	in_COMMIT_EVENT_ADDRESS ->write(0xd00);
1134	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00);
1135	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00);
1136	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
1137
1138	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1139
1140	do
1141	{
1142	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1143
1144	SC_START(1);
1145	}
1146	while (not ( in_COMMIT_EVENT_VAL ->read() and
1147	out_COMMIT_EVENT_ACK ->read()));
1148	in_COMMIT_EVENT_VAL ->write(0);
1149
1150	LABEL("exception (wait end)");
1151	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1152
1153	SC_START(3);
1154
1155	in_NB_INST_DECOD_ALL [context]->write(0);
1156	in_NB_INST_COMMIT_ALL [context]->write(0);
1157	in_NB_INST_COMMIT_MEM [context]->write(0);
1158
1159	SC_START(1);
1160
1161	LABEL("exception (wait event)");
1162
1163	bool find = false;
1164	do
1165	{
1166	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1167
1168	SC_START(0);
1169
1170	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1171	{
1172	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
1173	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
1174	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1175	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1176
1177	find = true;
1178	}
1179
1180	SC_START(1);
1181	}
1182	while (not find);
1183
1184	in_EVENT_ACK [context]->write(0);
1185
1186	LABEL("exception (wait spr)");
1187
1188	find = false;
1189	do
1190	{
1191	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1192
1193	SC_START(0);
1194
1195	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1196	{
1197	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00);
1198	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00);
1199	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1);
1200	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
1201	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1202
1203	find = true;
1204	}
1205
1206	SC_START(1);
1207	}
1208	while (not find);
1209
1210	in_SPR_EVENT_ACK [context]->write(0);
1211	}
1212
1213
1214	SC_START(1);
1215	}
1216
1217
1218	/********************************************************
1219	* Simulation - End
1220	********************************************************/
1221
1222	TEST_OK ("End of Simulation");
1223	delete _time;
1224
1225	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
1226
1227	delete in_CLOCK;
1228	delete in_NRESET;
1229
1230	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_VAL ,_param->_nb_context);
1231	DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context);
1232	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
1233	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
1234	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
1235	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
1236	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
1237	DELETE1_SC_SIGNAL( in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
1238	DELETE1_SC_SIGNAL(out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
1239	DELETE1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
1240	DELETE1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
1241	DELETE1_SC_SIGNAL( in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
1242	DELETE1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
1243	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
1244	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
1245	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_VAL );
1246	DELETE_SC_SIGNAL (out_COMMIT_EVENT_ACK );
1247	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID );
1248	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH );
1249	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_TYPE );
1250	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT );
1251	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS );
1252	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR );
1253	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
1254	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR );
1255	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
1256	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
1257	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
1258	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
1259	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
1260	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
1261	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
1262	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
1263	DELETE1_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_context );
1264	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context );
1265	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context );
1266	DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context );
1267	DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context );
1268	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context );
1269	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
1270	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
1271	DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context );
1272	DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context );
1273	DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context );
1274	DELETE1_SC_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context );
1275	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context );
1276	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context );
1277	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context );
1278	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context );
1279	DELETE1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
1280	DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context );
1281	DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context );
1282	DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context );
1283
1284	DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context );
1285	}
1286	#endif
1287
1288	delete _Context_State;
1289	#ifdef STATISTICS
1290	delete _parameters_statistics;
1291	#endif
1292	}

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