Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (15 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
r83 r88 48 48 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 49 49 50 ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_VAL ," in_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); 51 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,"out_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); 52 //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); 53 //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); 54 //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ," in_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context); 55 ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ," in_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); 56 ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ," in_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context); 57 50 58 ALLOC1_SC_SIGNAL( in_DECOD_EVENT_VAL ," in_DECOD_EVENT_VAL ",Tcontrol_t ,_param->_nb_decod_unit); 51 59 ALLOC1_SC_SIGNAL(out_DECOD_EVENT_ACK ,"out_DECOD_EVENT_ACK ",Tcontrol_t ,_param->_nb_decod_unit); … … 57 65 ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ," in_DECOD_EVENT_ADDRESS_EPCR ",Taddress_t ,_param->_nb_decod_unit); 58 66 59 ALLOC 1_SC_SIGNAL( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t ,_param->_nb_ooo_engine);60 ALLOC 1_SC_SIGNAL(out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t ,_param->_nb_ooo_engine);61 ALLOC 1_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_ooo_engine);62 ALLOC 1_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t ,_param->_nb_ooo_engine);63 ALLOC 1_SC_SIGNAL( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t,_param->_nb_ooo_engine);64 ALLOC 1_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_ooo_engine);65 ALLOC 1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t ,_param->_nb_ooo_engine);66 ALLOC 1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ,_param->_nb_ooo_engine);67 ALLOC 1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ,_param->_nb_ooo_engine);68 ALLOC 1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Taddress_t ,_param->_nb_ooo_engine);67 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t ); 68 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t ); 69 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t ); 70 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t ); 71 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t); 72 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); 73 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t ); 74 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); 75 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); 76 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Taddress_t ); 69 77 70 78 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); … … 78 86 79 87 80 ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_ decod_unit);81 ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_ ooo_engine);82 ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_ ooo_engine);88 ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context ); 89 ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context ); 90 ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context ); 83 91 84 92 ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context ); … … 89 97 ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context ); 90 98 91 ALLOC1_SC_SIGNAL(out_SPR_ VAL ,"out_SPR_VAL",Tcontrol_t ,_param->_nb_context );92 ALLOC1_SC_SIGNAL( in_SPR_ ACK ," in_SPR_ACK",Tcontrol_t ,_param->_nb_context );93 ALLOC1_SC_SIGNAL(out_SPR_E PCR ,"out_SPR_EPCR",Taddress_t ,_param->_nb_context );94 ALLOC1_SC_SIGNAL(out_SPR_E EAR ,"out_SPR_EEAR",Taddress_t ,_param->_nb_context );95 ALLOC1_SC_SIGNAL(out_SPR_E EAR_WEN ,"out_SPR_EEAR_WEN",Tcontrol_t ,_param->_nb_context );96 ALLOC1_SC_SIGNAL(out_SPR_ SR_DSX ,"out_SPR_SR_DSX",Tcontrol_t ,_param->_nb_context );97 ALLOC1_SC_SIGNAL(out_SPR_ SR_TO_ESR ,"out_SPR_SR_TO_ESR",Tcontrol_t ,_param->_nb_context );99 ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context ); 100 ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context ); 101 ALLOC1_SC_SIGNAL(out_SPR_EVENT_EPCR ,"out_SPR_EVENT_EPCR ",Taddress_t ,_param->_nb_context ); 102 ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR ,"out_SPR_EVENT_EEAR ",Taddress_t ,_param->_nb_context ); 103 ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,"out_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_context ); 104 ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,"out_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_context ); 105 ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,"out_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context ); 98 106 99 107 ALLOC1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,"out_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context ); 100 108 101 ALLOC1_SC_SIGNAL( in_DEPTH_ TAIL ," in_DEPTH_TAIL",Tdepth_t ,_param->_nb_context );109 ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context ); 102 110 111 ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context ); 112 ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context ); 113 114 ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_context ); 115 103 116 /******************************************************** 104 117 * Instanciation … … 110 123 (*(_Context_State->in_NRESET)) (*(in_NRESET)); 111 124 125 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_VAL ,_param->_nb_context); 126 INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_EVENT_ACK ,_param->_nb_context); 127 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); 128 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context); 129 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); 130 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); 131 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); 112 132 INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_VAL ,_param->_nb_decod_unit); 113 133 INSTANCE1_SC_SIGNAL(_Context_State,out_DECOD_EVENT_ACK ,_param->_nb_decod_unit); 114 134 if (_param->_have_port_context_id) 115 135 INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit); 116 if (_param->_have_port_ max_depth)136 if (_param->_have_port_depth) 117 137 INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit); 118 138 INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit); … … 121 141 INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit); 122 142 123 INSTANCE 1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_VAL ,_param->_nb_ooo_engine);124 INSTANCE 1_SC_SIGNAL(_Context_State,out_COMMIT_EVENT_ACK ,_param->_nb_ooo_engine);143 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_VAL ); 144 INSTANCE_SC_SIGNAL (_Context_State,out_COMMIT_EVENT_ACK ); 125 145 if (_param->_have_port_context_id) 126 INSTANCE 1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_CONTEXT_ID ,_param->_nb_ooo_engine);127 if (_param->_have_port_ max_depth)128 INSTANCE 1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_DEPTH ,_param->_nb_ooo_engine);129 INSTANCE 1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_TYPE ,_param->_nb_ooo_engine);130 INSTANCE 1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT ,_param->_nb_ooo_engine);131 INSTANCE 1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS ,_param->_nb_ooo_engine);132 INSTANCE 1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_nb_ooo_engine);133 INSTANCE 1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine);134 INSTANCE 1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR ,_param->_nb_ooo_engine);146 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_CONTEXT_ID ); 147 if (_param->_have_port_depth) 148 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_DEPTH ); 149 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_TYPE ); 150 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT ); 151 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS ); 152 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR ); 153 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); 154 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR ); 135 155 136 156 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); … … 138 158 if (_param->_have_port_context_id) 139 159 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); 140 if (_param->_have_port_ max_depth)160 if (_param->_have_port_depth) 141 161 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); 142 162 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); … … 145 165 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete); 146 166 147 INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_DECOD_ALL ,_param->_nb_ decod_unit);148 INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_ALL ,_param->_nb_ ooo_engine);149 INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_MEM ,_param->_nb_ ooo_engine);167 INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_DECOD_ALL ,_param->_nb_context ); 168 INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_ALL ,_param->_nb_context ); 169 INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_MEM ,_param->_nb_context ); 150 170 151 171 INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_VAL ,_param->_nb_context ); … … 156 176 INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_IS_DS_TAKE ,_param->_nb_context ); 157 177 158 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_ VAL,_param->_nb_context );159 INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_ ACK,_param->_nb_context );160 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_E PCR,_param->_nb_context );161 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_E EAR,_param->_nb_context );162 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_E EAR_WEN,_param->_nb_context );163 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_ SR_DSX,_param->_nb_context );164 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_ SR_TO_ESR,_param->_nb_context );178 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_VAL ,_param->_nb_context ); 179 INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_EVENT_ACK ,_param->_nb_context ); 180 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EPCR ,_param->_nb_context ); 181 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR ,_param->_nb_context ); 182 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR_WEN ,_param->_nb_context ); 183 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_DSX ,_param->_nb_context ); 184 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context ); 165 185 166 186 INSTANCE1_SC_SIGNAL(_Context_State,out_CONTEXT_DECOD_ENABLE ,_param->_nb_context ); 167 187 168 188 for (uint32_t i=0; i<_param->_nb_context; i++) 169 if (_param->_have_port_depth [i]) 170 INSTANCE_SC_SIGNAL(_Context_State, in_DEPTH_TAIL [i]); 189 if (_param->_have_port_depth) 190 INSTANCE_SC_SIGNAL(_Context_State, in_DEPTH_MIN [i]); 191 192 INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_IEE ,_param->_nb_context ); 193 INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_EPH ,_param->_nb_context ); 194 195 INSTANCE1_SC_SIGNAL(_Context_State, in_INTERRUPT_ENABLE ,_param->_nb_context ); 171 196 172 197 msg(_("<%s> : Start Simulation ............\n"),name.c_str()); … … 206 231 for (uint32_t i=0; i<_param->_nb_decod_unit; i++) 207 232 in_DECOD_EVENT_VAL [i]->write(0); 208 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 209 in_COMMIT_EVENT_VAL [i]->write(0); 233 in_COMMIT_EVENT_VAL ->write(0); 210 234 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 211 235 in_BRANCH_COMPLETE_VAL [i]->write(0); … … 213 237 for (uint32_t i=0; i<_param->_nb_context; i++) 214 238 { 215 in_EVENT_ACK [i]->write(0); 216 in_SPR_ACK [i]->write(0); 239 in_BRANCH_EVENT_VAL [i]->write(0); 240 in_EVENT_ACK [i]->write(0); 241 in_SPR_EVENT_ACK [i]->write(0); 242 in_SPR_SR_IEE [i]->write(0); 243 in_SPR_SR_EPH [i]->write(0); 244 in_INTERRUPT_ENABLE [i]->write(0); 217 245 218 246 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[i]->read(), 1); … … 220 248 221 249 for (uint32_t i=0; i<_param->_nb_context; i++) 222 if (_param->_have_port_depth [i])223 in_DEPTH_ TAIL [i]->write(i%_param->_size_depth[i]);250 if (_param->_have_port_depth) 251 in_DEPTH_MIN [i]->write((_param->_array_size_depth[i]==0)?0:(i%_param->_array_size_depth[i])); 224 252 225 253 uint32_t context = rand()%_param->_nb_context; 226 uint32_t decod_unit = _param->_link_context_to_decod_unit [context];227 uint32_t ooo_engine = _param->_link_decod_unit_to_ooo_engine [decod_unit];228 254 229 255 if (1) … … 232 258 233 259 LABEL("msync (begin)"); 234 in_NB_INST_DECOD_ALL [ decod_unit]->write(1);235 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(1);236 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(1);260 in_NB_INST_DECOD_ALL [context]->write(1); 261 in_NB_INST_COMMIT_ALL [context]->write(1); 262 in_NB_INST_COMMIT_MEM [context]->write(1); 237 263 238 264 uint32_t port = rand()%_param->_nb_decod_unit; … … 242 268 in_DECOD_EVENT_ADDRESS [port]->write(0x100); 243 269 in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef); 244 if (_param->_have_port_depth [context])245 in_DECOD_EVENT_DEPTH [port]->write(( context+1)%_param->_size_depth[context]);270 if (_param->_have_port_depth) 271 in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 246 272 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_MSYNC); 247 273 … … 263 289 SC_START(3); 264 290 265 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);266 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(1);267 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(0);291 in_NB_INST_DECOD_ALL [context]->write(0); 292 in_NB_INST_COMMIT_ALL [context]->write(1); 293 in_NB_INST_COMMIT_MEM [context]->write(0); 268 294 269 295 SC_START(1); … … 274 300 SC_START(3); 275 301 276 in_NB_INST_DECOD_ALL [ decod_unit]->write(1);302 in_NB_INST_DECOD_ALL [context]->write(1); 277 303 SC_START(1); 278 304 279 305 LABEL("msync (wait end)"); 280 306 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); 281 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);282 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(1);283 284 SC_START(3); 285 286 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(0);307 in_NB_INST_DECOD_ALL [context]->write(0); 308 in_NB_INST_COMMIT_MEM [context]->write(1); 309 310 SC_START(3); 311 312 in_NB_INST_COMMIT_MEM [context]->write(0); 287 313 SC_START(1); 288 314 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); … … 294 320 295 321 LABEL("psync (begin)"); 296 in_NB_INST_DECOD_ALL [ decod_unit]->write(1);297 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(1);298 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(1);322 in_NB_INST_DECOD_ALL [context]->write(1); 323 in_NB_INST_COMMIT_ALL [context]->write(1); 324 in_NB_INST_COMMIT_MEM [context]->write(1); 299 325 300 326 uint32_t port = rand()%_param->_nb_decod_unit; … … 304 330 in_DECOD_EVENT_ADDRESS [port]->write(0x200); 305 331 in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe); 306 if (_param->_have_port_depth [context])307 in_DECOD_EVENT_DEPTH [port]->write((context+1)%_param->_size_depth[context]);332 if (_param->_have_port_depth) 333 in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 308 334 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC); 309 335 … … 325 351 SC_START(3); 326 352 327 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);328 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(0);329 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(0);353 in_NB_INST_DECOD_ALL [context]->write(0); 354 in_NB_INST_COMMIT_ALL [context]->write(0); 355 in_NB_INST_COMMIT_MEM [context]->write(0); 330 356 331 357 SC_START(1); … … 361 387 362 388 LABEL("csync (begin)"); 363 in_NB_INST_DECOD_ALL [ decod_unit]->write(1);364 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(1);365 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(1);389 in_NB_INST_DECOD_ALL [context]->write(1); 390 in_NB_INST_COMMIT_ALL [context]->write(1); 391 in_NB_INST_COMMIT_MEM [context]->write(1); 366 392 367 393 uint32_t port = rand()%_param->_nb_decod_unit; … … 371 397 in_DECOD_EVENT_ADDRESS [port]->write(0x200); 372 398 in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe); 373 if (_param->_have_port_depth [context])374 in_DECOD_EVENT_DEPTH [port]->write(( context+1)%_param->_size_depth[context]);399 if (_param->_have_port_depth) 400 in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 375 401 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC); 376 402 … … 392 418 SC_START(3); 393 419 394 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);395 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(0);396 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(0);420 in_NB_INST_DECOD_ALL [context]->write(0); 421 in_NB_INST_COMMIT_ALL [context]->write(0); 422 in_NB_INST_COMMIT_MEM [context]->write(0); 397 423 398 424 SC_START(1); … … 426 452 427 453 LABEL("spr (begin)"); 428 in_NB_INST_DECOD_ALL [ decod_unit]->write(1);429 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(1);430 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(1);454 in_NB_INST_DECOD_ALL [context]->write(1); 455 in_NB_INST_COMMIT_ALL [context]->write(1); 456 in_NB_INST_COMMIT_MEM [context]->write(1); 431 457 432 458 uint32_t port = rand()%_param->_nb_decod_unit; … … 436 462 in_DECOD_EVENT_ADDRESS [port]->write(0x100); 437 463 in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef); 438 if (_param->_have_port_depth [context])439 in_DECOD_EVENT_DEPTH [port]->write(( context+1)%_param->_size_depth[context]);464 if (_param->_have_port_depth) 465 in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 440 466 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_SPR_ACCESS); 441 467 … … 457 483 SC_START(3); 458 484 459 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);460 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(0);461 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(0);485 in_NB_INST_DECOD_ALL [context]->write(0); 486 in_NB_INST_COMMIT_ALL [context]->write(0); 487 in_NB_INST_COMMIT_MEM [context]->write(0); 462 488 463 489 SC_START(1); … … 468 494 SC_START(3); 469 495 470 in_NB_INST_DECOD_ALL [ decod_unit]->write(1);496 in_NB_INST_DECOD_ALL [context]->write(1); 471 497 SC_START(1); 472 498 473 499 LABEL("spr (wait end)"); 474 500 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); 475 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);476 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(1);477 478 SC_START(3); 479 480 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(0);501 in_NB_INST_DECOD_ALL [context]->write(0); 502 in_NB_INST_COMMIT_ALL [context]->write(1); 503 504 SC_START(3); 505 506 in_NB_INST_COMMIT_ALL [context]->write(0); 481 507 SC_START(1); 482 508 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); … … 488 514 489 515 LABEL("miss (begin)"); 490 in_NB_INST_DECOD_ALL [ decod_unit]->write(1);491 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(1);492 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(1);516 in_NB_INST_DECOD_ALL [context]->write(1); 517 in_NB_INST_COMMIT_ALL [context]->write(1); 518 in_NB_INST_COMMIT_MEM [context]->write(1); 493 519 494 520 uint32_t port = rand()%_param->_nb_inst_branch_complete; 495 521 496 522 in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); 497 if (_param->_have_port_depth [context])498 in_BRANCH_COMPLETE_DEPTH [port]->write(( context+1)%_param->_size_depth[context]);523 if (_param->_have_port_depth) 524 in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 499 525 in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400); 500 526 in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500); … … 519 545 SC_START(3); 520 546 521 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);522 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(0);523 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(0);547 in_NB_INST_DECOD_ALL [context]->write(0); 548 in_NB_INST_COMMIT_ALL [context]->write(0); 549 in_NB_INST_COMMIT_MEM [context]->write(0); 524 550 525 551 SC_START(1); … … 558 584 559 585 LABEL("miss (begin)"); 560 in_NB_INST_DECOD_ALL [ decod_unit]->write(1);561 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(1);562 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(1);586 in_NB_INST_DECOD_ALL [context]->write(1); 587 in_NB_INST_COMMIT_ALL [context]->write(1); 588 in_NB_INST_COMMIT_MEM [context]->write(1); 563 589 564 590 uint32_t port = rand()%_param->_nb_inst_branch_complete; 565 591 566 592 in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); 567 if (_param->_have_port_depth [context])568 in_BRANCH_COMPLETE_DEPTH [port]->write(( context+1)%_param->_size_depth[context]);593 if (_param->_have_port_depth) 594 in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 569 595 in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600); 570 596 in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700); … … 589 615 SC_START(3); 590 616 591 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);592 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(0);593 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(0);617 in_NB_INST_DECOD_ALL [context]->write(0); 618 in_NB_INST_COMMIT_ALL [context]->write(0); 619 in_NB_INST_COMMIT_MEM [context]->write(0); 594 620 595 621 SC_START(1); … … 626 652 627 653 LABEL("exception (begin)"); 628 in_NB_INST_DECOD_ALL [ decod_unit]->write(1);629 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(1);630 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(1);631 632 uint32_t port = rand()%_param->_nb_ ooo_engine;654 in_NB_INST_DECOD_ALL [context]->write(1); 655 in_NB_INST_COMMIT_ALL [context]->write(1); 656 in_NB_INST_COMMIT_MEM [context]->write(1); 657 658 uint32_t port = rand()%_param->_nb_decod_unit; 633 659 634 660 in_DECOD_EVENT_CONTEXT_ID [port]->write(context); 635 if (_param->_have_port_depth [context])636 in_DECOD_EVENT_DEPTH [port]->write(( context)%_param->_size_depth[context]);661 if (_param->_have_port_depth) 662 in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); 637 663 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); 638 664 in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0); … … 657 683 SC_START(3); 658 684 659 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);660 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(0);661 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(0);685 in_NB_INST_DECOD_ALL [context]->write(0); 686 in_NB_INST_COMMIT_ALL [context]->write(0); 687 in_NB_INST_COMMIT_MEM [context]->write(0); 662 688 663 689 SC_START(1); … … 693 719 do 694 720 { 695 in_SPR_ ACK [context]->write(rand()%percent_transaction_spr);696 697 SC_START(0); 698 699 if (out_SPR_ VAL [context]->read() and in_SPR_ACK [context]->read())700 { 701 TEST(Taddress_t,out_SPR_E PCR [context]->read(),0x900);702 //TEST(Taddress_t,out_SPR_E EAR [context]->read(),);703 TEST(Tcontrol_t,out_SPR_E EAR_WEN [context]->read(),0);704 TEST(Tcontrol_t,out_SPR_ SR_DSX [context]->read(),0);705 TEST(Tcontrol_t,out_SPR_ SR_TO_ESR [context]->read(),1);706 707 find = true; 708 } 709 710 SC_START(1); 711 } 712 while (not find); 713 714 in_SPR_ ACK [context]->write(0);721 in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr); 722 723 SC_START(0); 724 725 if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read()) 726 { 727 TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900); 728 //TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),); 729 TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0); 730 TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0); 731 TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1); 732 733 find = true; 734 } 735 736 SC_START(1); 737 } 738 while (not find); 739 740 in_SPR_EVENT_ACK [context]->write(0); 715 741 } 716 742 … … 720 746 721 747 LABEL("exception (begin)"); 722 in_NB_INST_DECOD_ALL [ decod_unit]->write(1);723 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(1);724 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(1);725 726 uint32_t port = rand()%_param->_nb_ ooo_engine;748 in_NB_INST_DECOD_ALL [context]->write(1); 749 in_NB_INST_COMMIT_ALL [context]->write(1); 750 in_NB_INST_COMMIT_MEM [context]->write(1); 751 752 uint32_t port = rand()%_param->_nb_decod_unit; 727 753 728 754 in_DECOD_EVENT_CONTEXT_ID [port]->write(context); 729 if (_param->_have_port_depth [context])730 in_DECOD_EVENT_DEPTH [port]->write(( context)%_param->_size_depth[context]);755 if (_param->_have_port_depth) 756 in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); 731 757 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); 732 758 in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(1); … … 751 777 SC_START(3); 752 778 753 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);754 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(0);755 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(0);779 in_NB_INST_DECOD_ALL [context]->write(0); 780 in_NB_INST_COMMIT_ALL [context]->write(0); 781 in_NB_INST_COMMIT_MEM [context]->write(0); 756 782 757 783 SC_START(1); … … 787 813 do 788 814 { 789 in_SPR_ ACK [context]->write(rand()%percent_transaction_spr);790 791 SC_START(0); 792 793 if (out_SPR_ VAL [context]->read() and in_SPR_ACK [context]->read())794 { 795 TEST(Taddress_t,out_SPR_E PCR [context]->read(),0x900);796 //TEST(Taddress_t,out_SPR_E EAR [context]->read(),);797 TEST(Tcontrol_t,out_SPR_E EAR_WEN [context]->read(),0);798 TEST(Tcontrol_t,out_SPR_ SR_DSX [context]->read(),1);799 TEST(Tcontrol_t,out_SPR_ SR_TO_ESR [context]->read(),1);800 801 find = true; 802 } 803 804 SC_START(1); 805 } 806 while (not find); 807 808 in_SPR_ ACK [context]->write(0);815 in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr); 816 817 SC_START(0); 818 819 if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read()) 820 { 821 TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900); 822 //TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),); 823 TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0); 824 TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1); 825 TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1); 826 827 find = true; 828 } 829 830 SC_START(1); 831 } 832 while (not find); 833 834 in_SPR_EVENT_ACK [context]->write(0); 809 835 } 810 836 … … 814 840 815 841 LABEL("exception (begin)"); 816 in_NB_INST_DECOD_ALL [decod_unit]->write(1); 817 in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); 818 in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); 819 820 uint32_t port = rand()%_param->_nb_ooo_engine; 821 822 in_COMMIT_EVENT_CONTEXT_ID [port]->write(context); 823 if (_param->_have_port_depth [context]) 824 in_COMMIT_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]); 825 in_COMMIT_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); 826 in_COMMIT_EVENT_IS_DELAY_SLOT [port]->write(0); 827 in_COMMIT_EVENT_ADDRESS [port]->write(0xa00); 828 in_COMMIT_EVENT_ADDRESS_EPCR [port]->write(0xb00); 829 in_COMMIT_EVENT_ADDRESS_EEAR [port]->write(0xc00); 830 in_COMMIT_EVENT_ADDRESS_EEAR_VAL [port]->write(0); 831 832 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 833 834 do 835 { 836 in_COMMIT_EVENT_VAL [port]->write(rand()%percent_transaction_commit_event); 837 838 SC_START(1); 839 } 840 while (not ( in_COMMIT_EVENT_VAL [port]->read() and 841 out_COMMIT_EVENT_ACK [port]->read())); 842 in_COMMIT_EVENT_VAL [port]->write(0); 842 in_NB_INST_DECOD_ALL [context]->write(1); 843 in_NB_INST_COMMIT_ALL [context]->write(1); 844 in_NB_INST_COMMIT_MEM [context]->write(1); 845 846 in_COMMIT_EVENT_CONTEXT_ID ->write(context); 847 if (_param->_have_port_depth) 848 in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); 849 in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); 850 in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0); 851 in_COMMIT_EVENT_ADDRESS ->write(0xa00); 852 in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00); 853 in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00); 854 in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0); 855 856 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 857 858 do 859 { 860 in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event); 861 862 SC_START(1); 863 } 864 while (not ( in_COMMIT_EVENT_VAL ->read() and 865 out_COMMIT_EVENT_ACK ->read())); 866 in_COMMIT_EVENT_VAL ->write(0); 843 867 844 868 LABEL("exception (wait end)"); … … 847 871 SC_START(3); 848 872 849 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);850 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(0);851 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(0);873 in_NB_INST_DECOD_ALL [context]->write(0); 874 in_NB_INST_COMMIT_ALL [context]->write(0); 875 in_NB_INST_COMMIT_MEM [context]->write(0); 852 876 853 877 SC_START(1); … … 883 907 do 884 908 { 885 in_SPR_ ACK [context]->write(rand()%percent_transaction_spr);886 887 SC_START(0); 888 889 if (out_SPR_ VAL [context]->read() and in_SPR_ACK [context]->read())890 { 891 TEST(Taddress_t,out_SPR_E PCR [context]->read(),0xb00);892 TEST(Taddress_t,out_SPR_E EAR [context]->read(),0xc00);893 TEST(Tcontrol_t,out_SPR_E EAR_WEN [context]->read(),0);894 TEST(Tcontrol_t,out_SPR_ SR_DSX [context]->read(),0);895 TEST(Tcontrol_t,out_SPR_ SR_TO_ESR [context]->read(),1);896 897 find = true; 898 } 899 900 SC_START(1); 901 } 902 while (not find); 903 904 in_SPR_ ACK [context]->write(0);909 in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr); 910 911 SC_START(0); 912 913 if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read()) 914 { 915 TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00); 916 TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00); 917 TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0); 918 TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0); 919 TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1); 920 921 find = true; 922 } 923 924 SC_START(1); 925 } 926 while (not find); 927 928 in_SPR_EVENT_ACK [context]->write(0); 905 929 } 906 930 … … 910 934 911 935 LABEL("exception (begin)"); 912 in_NB_INST_DECOD_ALL [decod_unit]->write(1); 913 in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); 914 in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); 915 916 uint32_t port = rand()%_param->_nb_ooo_engine; 917 918 in_COMMIT_EVENT_CONTEXT_ID [port]->write(context); 919 if (_param->_have_port_depth [context]) 920 in_COMMIT_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]); 921 in_COMMIT_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); 922 in_COMMIT_EVENT_IS_DELAY_SLOT [port]->write(1); 923 in_COMMIT_EVENT_ADDRESS [port]->write(0xd00); 924 in_COMMIT_EVENT_ADDRESS_EPCR [port]->write(0xe00); 925 in_COMMIT_EVENT_ADDRESS_EEAR [port]->write(0xf00); 926 in_COMMIT_EVENT_ADDRESS_EEAR_VAL [port]->write(0); 927 928 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 929 930 do 931 { 932 in_COMMIT_EVENT_VAL [port]->write(rand()%percent_transaction_commit_event); 933 934 SC_START(1); 935 } 936 while (not ( in_COMMIT_EVENT_VAL [port]->read() and 937 out_COMMIT_EVENT_ACK [port]->read())); 938 in_COMMIT_EVENT_VAL [port]->write(0); 936 in_NB_INST_DECOD_ALL [context]->write(1); 937 in_NB_INST_COMMIT_ALL [context]->write(1); 938 in_NB_INST_COMMIT_MEM [context]->write(1); 939 940 in_COMMIT_EVENT_CONTEXT_ID ->write(context); 941 if (_param->_have_port_depth) 942 in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); 943 in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); 944 in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1); 945 in_COMMIT_EVENT_ADDRESS ->write(0xd00); 946 in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00); 947 in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00); 948 in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0); 949 950 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 951 952 do 953 { 954 in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event); 955 956 SC_START(1); 957 } 958 while (not ( in_COMMIT_EVENT_VAL ->read() and 959 out_COMMIT_EVENT_ACK ->read())); 960 in_COMMIT_EVENT_VAL ->write(0); 939 961 940 962 LABEL("exception (wait end)"); … … 943 965 SC_START(3); 944 966 945 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);946 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(0);947 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(0);967 in_NB_INST_DECOD_ALL [context]->write(0); 968 in_NB_INST_COMMIT_ALL [context]->write(0); 969 in_NB_INST_COMMIT_MEM [context]->write(0); 948 970 949 971 SC_START(1); … … 979 1001 do 980 1002 { 981 in_SPR_ ACK [context]->write(rand()%percent_transaction_spr);982 983 SC_START(0); 984 985 if (out_SPR_ VAL [context]->read() and in_SPR_ACK [context]->read())986 { 987 TEST(Taddress_t,out_SPR_E PCR [context]->read(),0xe00);988 TEST(Taddress_t,out_SPR_E EAR [context]->read(),0xf00);989 TEST(Tcontrol_t,out_SPR_E EAR_WEN [context]->read(),0);990 TEST(Tcontrol_t,out_SPR_ SR_DSX [context]->read(),1);991 TEST(Tcontrol_t,out_SPR_ SR_TO_ESR [context]->read(),1);992 993 find = true; 994 } 995 996 SC_START(1); 997 } 998 while (not find); 999 1000 in_SPR_ ACK [context]->write(0);1003 in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr); 1004 1005 SC_START(0); 1006 1007 if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read()) 1008 { 1009 TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00); 1010 TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00); 1011 TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0); 1012 TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1); 1013 TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1); 1014 1015 find = true; 1016 } 1017 1018 SC_START(1); 1019 } 1020 while (not find); 1021 1022 in_SPR_EVENT_ACK [context]->write(0); 1001 1023 } 1002 1024 … … 1006 1028 1007 1029 LABEL("exception (begin)"); 1008 in_NB_INST_DECOD_ALL [decod_unit]->write(1); 1009 in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); 1010 in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); 1011 1012 uint32_t port = rand()%_param->_nb_ooo_engine; 1013 1014 in_COMMIT_EVENT_CONTEXT_ID [port]->write(context); 1015 if (_param->_have_port_depth [context]) 1016 in_COMMIT_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]); 1017 in_COMMIT_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); 1018 in_COMMIT_EVENT_IS_DELAY_SLOT [port]->write(0); 1019 in_COMMIT_EVENT_ADDRESS [port]->write(0xa00); 1020 in_COMMIT_EVENT_ADDRESS_EPCR [port]->write(0xb00); 1021 in_COMMIT_EVENT_ADDRESS_EEAR [port]->write(0xc00); 1022 in_COMMIT_EVENT_ADDRESS_EEAR_VAL [port]->write(1); 1023 1024 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 1025 1026 do 1027 { 1028 in_COMMIT_EVENT_VAL [port]->write(rand()%percent_transaction_commit_event); 1029 1030 SC_START(1); 1031 } 1032 while (not ( in_COMMIT_EVENT_VAL [port]->read() and 1033 out_COMMIT_EVENT_ACK [port]->read())); 1034 in_COMMIT_EVENT_VAL [port]->write(0); 1030 in_NB_INST_DECOD_ALL [context]->write(1); 1031 in_NB_INST_COMMIT_ALL [context]->write(1); 1032 in_NB_INST_COMMIT_MEM [context]->write(1); 1033 1034 in_COMMIT_EVENT_CONTEXT_ID ->write(context); 1035 if (_param->_have_port_depth) 1036 in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); 1037 in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); 1038 in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0); 1039 in_COMMIT_EVENT_ADDRESS ->write(0xa00); 1040 in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00); 1041 in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00); 1042 in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1); 1043 1044 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 1045 1046 do 1047 { 1048 in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event); 1049 1050 SC_START(1); 1051 } 1052 while (not ( in_COMMIT_EVENT_VAL ->read() and 1053 out_COMMIT_EVENT_ACK ->read())); 1054 in_COMMIT_EVENT_VAL ->write(0); 1035 1055 1036 1056 LABEL("exception (wait end)"); … … 1039 1059 SC_START(3); 1040 1060 1041 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);1042 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(0);1043 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(0);1061 in_NB_INST_DECOD_ALL [context]->write(0); 1062 in_NB_INST_COMMIT_ALL [context]->write(0); 1063 in_NB_INST_COMMIT_MEM [context]->write(0); 1044 1064 1045 1065 SC_START(1); … … 1075 1095 do 1076 1096 { 1077 in_SPR_ ACK [context]->write(rand()%percent_transaction_spr);1078 1079 SC_START(0); 1080 1081 if (out_SPR_ VAL [context]->read() and in_SPR_ACK [context]->read())1082 { 1083 TEST(Taddress_t,out_SPR_E PCR [context]->read(),0xb00);1084 TEST(Taddress_t,out_SPR_E EAR [context]->read(),0xc00);1085 TEST(Tcontrol_t,out_SPR_E EAR_WEN [context]->read(),1);1086 TEST(Tcontrol_t,out_SPR_ SR_DSX [context]->read(),0);1087 TEST(Tcontrol_t,out_SPR_ SR_TO_ESR [context]->read(),1);1088 1089 find = true; 1090 } 1091 1092 SC_START(1); 1093 } 1094 while (not find); 1095 1096 in_SPR_ ACK [context]->write(0);1097 in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr); 1098 1099 SC_START(0); 1100 1101 if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read()) 1102 { 1103 TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00); 1104 TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00); 1105 TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1); 1106 TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0); 1107 TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1); 1108 1109 find = true; 1110 } 1111 1112 SC_START(1); 1113 } 1114 while (not find); 1115 1116 in_SPR_EVENT_ACK [context]->write(0); 1097 1117 } 1098 1118 … … 1102 1122 1103 1123 LABEL("exception (begin)"); 1104 in_NB_INST_DECOD_ALL [decod_unit]->write(1); 1105 in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); 1106 in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); 1107 1108 uint32_t port = rand()%_param->_nb_ooo_engine; 1109 1110 in_COMMIT_EVENT_CONTEXT_ID [port]->write(context); 1111 if (_param->_have_port_depth [context]) 1112 in_COMMIT_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]); 1113 in_COMMIT_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); 1114 in_COMMIT_EVENT_IS_DELAY_SLOT [port]->write(1); 1115 in_COMMIT_EVENT_ADDRESS [port]->write(0xd00); 1116 in_COMMIT_EVENT_ADDRESS_EPCR [port]->write(0xe00); 1117 in_COMMIT_EVENT_ADDRESS_EEAR [port]->write(0xf00); 1118 in_COMMIT_EVENT_ADDRESS_EEAR_VAL [port]->write(1); 1119 1120 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 1121 1122 do 1123 { 1124 in_COMMIT_EVENT_VAL [port]->write(rand()%percent_transaction_commit_event); 1125 1126 SC_START(1); 1127 } 1128 while (not ( in_COMMIT_EVENT_VAL [port]->read() and 1129 out_COMMIT_EVENT_ACK [port]->read())); 1130 in_COMMIT_EVENT_VAL [port]->write(0); 1124 in_NB_INST_DECOD_ALL [context]->write(1); 1125 in_NB_INST_COMMIT_ALL [context]->write(1); 1126 in_NB_INST_COMMIT_MEM [context]->write(1); 1127 1128 in_COMMIT_EVENT_CONTEXT_ID ->write(context); 1129 if (_param->_have_port_depth) 1130 in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); 1131 in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); 1132 in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1); 1133 in_COMMIT_EVENT_ADDRESS ->write(0xd00); 1134 in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00); 1135 in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00); 1136 in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1); 1137 1138 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 1139 1140 do 1141 { 1142 in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event); 1143 1144 SC_START(1); 1145 } 1146 while (not ( in_COMMIT_EVENT_VAL ->read() and 1147 out_COMMIT_EVENT_ACK ->read())); 1148 in_COMMIT_EVENT_VAL ->write(0); 1131 1149 1132 1150 LABEL("exception (wait end)"); … … 1135 1153 SC_START(3); 1136 1154 1137 in_NB_INST_DECOD_ALL [ decod_unit]->write(0);1138 in_NB_INST_COMMIT_ALL [ ooo_engine]->write(0);1139 in_NB_INST_COMMIT_MEM [ ooo_engine]->write(0);1155 in_NB_INST_DECOD_ALL [context]->write(0); 1156 in_NB_INST_COMMIT_ALL [context]->write(0); 1157 in_NB_INST_COMMIT_MEM [context]->write(0); 1140 1158 1141 1159 SC_START(1); … … 1171 1189 do 1172 1190 { 1173 in_SPR_ ACK [context]->write(rand()%percent_transaction_spr);1174 1175 SC_START(0); 1176 1177 if (out_SPR_ VAL [context]->read() and in_SPR_ACK [context]->read())1178 { 1179 TEST(Taddress_t,out_SPR_E PCR [context]->read(),0xe00);1180 TEST(Taddress_t,out_SPR_E EAR [context]->read(),0xf00);1181 TEST(Tcontrol_t,out_SPR_E EAR_WEN [context]->read(),1);1182 TEST(Tcontrol_t,out_SPR_ SR_DSX [context]->read(),1);1183 TEST(Tcontrol_t,out_SPR_ SR_TO_ESR [context]->read(),1);1184 1185 find = true; 1186 } 1187 1188 SC_START(1); 1189 } 1190 while (not find); 1191 1192 in_SPR_ ACK [context]->write(0);1191 in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr); 1192 1193 SC_START(0); 1194 1195 if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read()) 1196 { 1197 TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00); 1198 TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00); 1199 TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1); 1200 TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1); 1201 TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1); 1202 1203 find = true; 1204 } 1205 1206 SC_START(1); 1207 } 1208 while (not find); 1209 1210 in_SPR_EVENT_ACK [context]->write(0); 1193 1211 } 1194 1212 … … 1210 1228 delete in_NRESET; 1211 1229 1230 DELETE1_SC_SIGNAL( in_BRANCH_EVENT_VAL ,_param->_nb_context); 1231 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context); 1232 //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); 1233 //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context); 1234 //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); 1235 DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); 1236 DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); 1212 1237 DELETE1_SC_SIGNAL( in_DECOD_EVENT_VAL ,_param->_nb_decod_unit); 1213 1238 DELETE1_SC_SIGNAL(out_DECOD_EVENT_ACK ,_param->_nb_decod_unit); … … 1218 1243 DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit); 1219 1244 DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit); 1220 DELETE 1_SC_SIGNAL( in_COMMIT_EVENT_VAL ,_param->_nb_ooo_engine);1221 DELETE 1_SC_SIGNAL(out_COMMIT_EVENT_ACK ,_param->_nb_ooo_engine);1222 DELETE 1_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ,_param->_nb_ooo_engine);1223 DELETE 1_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ,_param->_nb_ooo_engine);1224 DELETE 1_SC_SIGNAL( in_COMMIT_EVENT_TYPE ,_param->_nb_ooo_engine);1225 DELETE 1_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ,_param->_nb_ooo_engine);1226 DELETE 1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ,_param->_nb_ooo_engine);1227 DELETE 1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_nb_ooo_engine);1228 DELETE 1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine);1229 DELETE 1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ,_param->_nb_ooo_engine);1245 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_VAL ); 1246 DELETE_SC_SIGNAL (out_COMMIT_EVENT_ACK ); 1247 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ); 1248 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH ); 1249 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_TYPE ); 1250 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ); 1251 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ); 1252 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ); 1253 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); 1254 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ); 1230 1255 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); 1231 1256 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); … … 1236 1261 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete); 1237 1262 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete); 1238 DELETE1_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_ decod_unit);1239 DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_ ooo_engine);1240 DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_ ooo_engine);1263 DELETE1_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_context ); 1264 DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context ); 1265 DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context ); 1241 1266 DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context ); 1242 1267 DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context ); … … 1245 1270 DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context ); 1246 1271 DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context ); 1247 DELETE1_SC_SIGNAL(out_SPR_ VAL,_param->_nb_context );1248 DELETE1_SC_SIGNAL( in_SPR_ ACK,_param->_nb_context );1249 DELETE1_SC_SIGNAL(out_SPR_E PCR,_param->_nb_context );1250 DELETE1_SC_SIGNAL(out_SPR_E EAR,_param->_nb_context );1251 DELETE1_SC_SIGNAL(out_SPR_E EAR_WEN,_param->_nb_context );1252 DELETE1_SC_SIGNAL(out_SPR_ SR_DSX,_param->_nb_context );1253 DELETE1_SC_SIGNAL(out_SPR_ SR_TO_ESR,_param->_nb_context );1272 DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context ); 1273 DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context ); 1274 DELETE1_SC_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context ); 1275 DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context ); 1276 DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context ); 1277 DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context ); 1278 DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context ); 1254 1279 DELETE1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,_param->_nb_context ); 1255 DELETE1_SC_SIGNAL( in_DEPTH_TAIL ,_param->_nb_context ); 1280 DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context ); 1281 DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context ); 1282 DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context ); 1283 1284 DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context ); 1256 1285 } 1257 1286 #endif
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