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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp @ 105

Last change on this file since 105 was 105, checked in by rosiere, 15 years ago
1) Bug fix : Load Miss Speculation (in Commit_unit, Update Prediction Table and Context State) 2) Change address, in rob write address_next. 3) Move Meta_Predictor in save directory
Property svn:keywords set to `Id`
File size: 5.6 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Context_State_genMoore.cpp 105 2009-02-05 11:18:31Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace context_state {
17
18
19	#undef FUNCTION
20	#define FUNCTION "Context_State::genMoore"
21	void Context_State::genMoore (void)
22	{
23	log_begin(Context_State,FUNCTION);
24	log_function(Context_State,FUNCTION,_name.c_str());
25
26	// -------------------------------------------------------------------
27	// -----[ EVENT ]-----------------------------------------------------
28	// -------------------------------------------------------------------
29	for (uint32_t i=0; i<_param->_nb_context; i++)
30	{
31	context_state_t state = reg_STATE [i];
32
33	Tcontrol_t val = ((state == CONTEXT_STATE_KO_EXCEP_ADDR ) or
34	(state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or
35	(state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or
36	(state == CONTEXT_STATE_KO_PSYNC_ADDR ) or
37	(state == CONTEXT_STATE_KO_CSYNC_ADDR));
38
39	// SR can't change in this cycle
40	// Exception Prefix High
41	Taddress_t address = reg_EVENT_ADDRESS [i] \| (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0);
42	Taddress_t address_next = reg_EVENT_ADDRESS_EPCR [i];
43	Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);
44	Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_IS_DS_TAKE [i]);
45	// excep : address exception
46	// miss : address delay_slot, and address dest
47	// psync : address next
48	// csync : address next
49	Tevent_type_t type ;//[nb_context]
50	Tdepth_t depth = reg_EVENT_DEPTH [i];
51
52	switch (state)
53	{
54	case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break;
55	case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: (type = EVENT_TYPE_BRANCH_MISS_SPECULATION); break;
56	case CONTEXT_STATE_KO_MISS_LOAD_ADDR : (type = EVENT_TYPE_LOAD_MISS_SPECULATION ); break;
57	case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC ); break;
58	case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC ); break;
59	default : (type = EVENT_TYPE_NONE ); break;
60	}
61	// (type = EVENT_TYPE_SPR_ACCESS );
62	// (type = EVENT_TYPE_MSYNC );
63	// (type = EVENT_TYPE_BRANCH_NO_ACCURATE);
64
65	internal_EVENT_VAL [i] = val;
66	PORT_WRITE(out_EVENT_VAL [i], val);
67	PORT_WRITE(out_EVENT_ADDRESS [i], address);
68	PORT_WRITE(out_EVENT_ADDRESS_NEXT [i], address_next);
69	PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], address_next_val);
70	PORT_WRITE(out_EVENT_IS_DS_TAKE [i], is_ds_take);
71	PORT_WRITE(out_EVENT_TYPE [i], type);
72	if (_param->_have_port_depth)
73	PORT_WRITE(out_EVENT_DEPTH [i], depth);
74
75	log_printf(TRACE,Context_State,FUNCTION," * EVENT Context : %d", i);
76	log_printf(TRACE,Context_State,FUNCTION," * VAL : %d", val);
77	log_printf(TRACE,Context_State,FUNCTION," * ADDRESS : %.8x (%.8x)", address , address <<2);
78	log_printf(TRACE,Context_State,FUNCTION," * ADDRESS_NEXT : %.8x (%.8x)", address_next, address_next<<2);
79	log_printf(TRACE,Context_State,FUNCTION," * ADDRESS_NEXT_VAL : %d", address_next_val);
80	log_printf(TRACE,Context_State,FUNCTION," * IS_DS_TAKE : %d", is_ds_take);
81	log_printf(TRACE,Context_State,FUNCTION," * TYPE : %d", type);
82	log_printf(TRACE,Context_State,FUNCTION," * DEPTH : %d", depth);
83	}
84
85	// -------------------------------------------------------------------
86	// -----[ SPR_EVENT ]-------------------------------------------------
87	// -------------------------------------------------------------------
88	for (uint32_t i=0; i<_param->_nb_context; i++)
89	{
90	context_state_t state = reg_STATE [i];
91
92	internal_SPR_EVENT_VAL [i] = (state == CONTEXT_STATE_KO_EXCEP_SPR );
93
94	PORT_WRITE(out_SPR_EVENT_VAL [i], internal_SPR_EVENT_VAL [i]);
95	PORT_WRITE(out_SPR_EVENT_EPCR [i], reg_EVENT_ADDRESS_EPCR [i]);
96	PORT_WRITE(out_SPR_EVENT_EEAR [i], reg_EVENT_ADDRESS_EEAR [i]);
97	PORT_WRITE(out_SPR_EVENT_EEAR_WEN [i], reg_EVENT_ADDRESS_EEAR_VAL [i]);
98	PORT_WRITE(out_SPR_EVENT_SR_DSX [i], reg_EVENT_IS_DELAY_SLOT [i]);
99	PORT_WRITE(out_SPR_EVENT_SR_TO_ESR [i], 1);
100	}
101
102	// -------------------------------------------------------------------
103	// -----[ CONTEXT ]---------------------------------------------------
104	// -------------------------------------------------------------------
105	for (uint32_t i=0; i<_param->_nb_context; i++)
106	{
107	context_state_t state = reg_STATE [i];
108
109	// PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], ((state==CONTEXT_STATE_OK ) or
110	// (state==CONTEXT_STATE_KO_MSYNC_ISSUE) or
111	// (state==CONTEXT_STATE_KO_SPR_ISSUE )));
112	PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], (state==CONTEXT_STATE_OK));
113	}
114
115	log_end(Context_State,FUNCTION);
116	};
117
118	}; // end namespace context_state
119	}; // end namespace front_end
120	}; // end namespace multi_front_end
121	}; // end namespace core
122
123	}; // end namespace behavioural
124	}; // end namespace morpheo
125	#endif

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