source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp @ 111

Last change on this file since 111 was 111, checked in by rosiere, 15 years ago

1) Decod_queue : multi implementation (one_fifo, multi_fifo)
2) Issue_queue : multi implementation (in_order, out_of_order)
3) Direction : Add Meta predictor
4) Context_State : re add Branch_complete, More priority to Load miss (is not speculative)
5) Return_Address_Stack : update reg_PREDICT pointer on decod miss prediction
6) UPT : Fix bug in multi event
7) Prediction_glue : in read_stack case, insert in UPT pc_next
8) Rename select : when rob have an event (need flush), read_r{a,b,c} and write_r{d,e} is set at 0
  • Property svn:keywords set to Id
File size: 5.8 KB
Line 
1#ifdef SYSTEMC
2/*
3 * $Id: Context_State_genMoore.cpp 111 2009-02-27 18:37:40Z rosiere $
4 *
5 * [ Description ]
6 *
7 */
8
9#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_front_end {
15namespace front_end {
16namespace context_state {
17
18
19#undef  FUNCTION
20#define FUNCTION "Context_State::genMoore"
21  void Context_State::genMoore (void)
22  {
23    log_begin(Context_State,FUNCTION);
24    log_function(Context_State,FUNCTION,_name.c_str());
25
26    // -------------------------------------------------------------------
27    // -----[ EVENT ]-----------------------------------------------------
28    // -------------------------------------------------------------------
29    for (uint32_t i=0; i<_param->_nb_context; i++)
30      {
31        context_state_t state = reg_STATE [i];
32
33        Tcontrol_t val              = ((state == CONTEXT_STATE_KO_EXCEP_ADDR      ) or
34                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or
35                                       (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR) or
36                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR  ) or
37                                       (state == CONTEXT_STATE_KO_PSYNC_ADDR      ) or
38                                       (state == CONTEXT_STATE_KO_CSYNC_ADDR));
39       
40        // SR can't change in this cycle
41        // Exception Prefix High
42        Taddress_t    address          = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0);
43        Taddress_t    address_next     = reg_EVENT_ADDRESS_EPCR [i];
44        Tcontrol_t    address_next_val = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);
45        Tcontrol_t    is_ds_take       = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]);
46        // excep : address exception
47        // miss  : address delay_slot, and address dest
48        // psync : address next
49        // csync : address next
50        Tevent_type_t type                         ;//[nb_context]
51        Tdepth_t      depth            = reg_EVENT_DEPTH [i];
52
53        switch (state)
54          {
55          case CONTEXT_STATE_KO_EXCEP_ADDR      : (type = EVENT_TYPE_EXCEPTION              ); break;
56          case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR: 
57          case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: (type = EVENT_TYPE_BRANCH_MISS_SPECULATION); break;
58          case CONTEXT_STATE_KO_MISS_LOAD_ADDR  : (type = EVENT_TYPE_LOAD_MISS_SPECULATION  ); break;
59          case CONTEXT_STATE_KO_PSYNC_ADDR      : (type = EVENT_TYPE_PSYNC                  ); break; 
60          case CONTEXT_STATE_KO_CSYNC_ADDR      : (type = EVENT_TYPE_CSYNC                  ); break;
61          default                               : (type = EVENT_TYPE_NONE                   ); break;
62          }
63//      (type = EVENT_TYPE_SPR_ACCESS        );
64//      (type = EVENT_TYPE_MSYNC             );
65//      (type = EVENT_TYPE_BRANCH_NO_ACCURATE);
66
67        internal_EVENT_VAL [i] = val;
68        PORT_WRITE(out_EVENT_VAL              [i], val);
69        PORT_WRITE(out_EVENT_ADDRESS          [i], address);
70        PORT_WRITE(out_EVENT_ADDRESS_NEXT     [i], address_next); 
71        PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], address_next_val);
72        PORT_WRITE(out_EVENT_IS_DS_TAKE       [i], is_ds_take);
73        PORT_WRITE(out_EVENT_TYPE             [i], type);
74        if (_param->_have_port_depth)
75        PORT_WRITE(out_EVENT_DEPTH            [i], depth);
76
77        log_printf(TRACE,Context_State,FUNCTION,"  * EVENT Context      : %d", i);
78        log_printf(TRACE,Context_State,FUNCTION,"    * VAL              : %d", val);
79        log_printf(TRACE,Context_State,FUNCTION,"    * ADDRESS          : %.8x (%.8x)", address     , address     <<2);
80        log_printf(TRACE,Context_State,FUNCTION,"    * ADDRESS_NEXT     : %.8x (%.8x)", address_next, address_next<<2); 
81        log_printf(TRACE,Context_State,FUNCTION,"    * ADDRESS_NEXT_VAL : %d", address_next_val);
82        log_printf(TRACE,Context_State,FUNCTION,"    * IS_DS_TAKE       : %d", is_ds_take);
83        log_printf(TRACE,Context_State,FUNCTION,"    * TYPE             : %d", type);
84        log_printf(TRACE,Context_State,FUNCTION,"    * DEPTH            : %d", depth);
85      }
86
87    // -------------------------------------------------------------------
88    // -----[ SPR_EVENT ]-------------------------------------------------
89    // -------------------------------------------------------------------
90    for (uint32_t i=0; i<_param->_nb_context; i++)
91      {
92        context_state_t state = reg_STATE [i];
93
94        internal_SPR_EVENT_VAL [i] = (state == CONTEXT_STATE_KO_EXCEP_SPR  );
95
96        PORT_WRITE(out_SPR_EVENT_VAL       [i], internal_SPR_EVENT_VAL     [i]);
97        PORT_WRITE(out_SPR_EVENT_EPCR      [i], reg_EVENT_ADDRESS_EPCR     [i]);
98        PORT_WRITE(out_SPR_EVENT_EEAR      [i], reg_EVENT_ADDRESS_EEAR     [i]);
99        PORT_WRITE(out_SPR_EVENT_EEAR_WEN  [i], reg_EVENT_ADDRESS_EEAR_VAL [i]);
100        PORT_WRITE(out_SPR_EVENT_SR_DSX    [i], reg_EVENT_IS_DELAY_SLOT    [i]);
101        PORT_WRITE(out_SPR_EVENT_SR_TO_ESR [i], 1);
102      }
103
104    // -------------------------------------------------------------------
105    // -----[ CONTEXT ]---------------------------------------------------
106    // -------------------------------------------------------------------
107    for (uint32_t i=0; i<_param->_nb_context; i++)
108      {
109        context_state_t state = reg_STATE [i];
110
111//      PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], ((state==CONTEXT_STATE_OK            ) or
112//                                                (state==CONTEXT_STATE_KO_MSYNC_ISSUE) or
113//                                                (state==CONTEXT_STATE_KO_SPR_ISSUE  )));
114        PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], (state==CONTEXT_STATE_OK));
115      }
116
117    log_end(Context_State,FUNCTION);
118  };
119
120}; // end namespace context_state
121}; // end namespace front_end
122}; // end namespace multi_front_end
123}; // end namespace core
124
125}; // end namespace behavioural
126}; // end namespace morpheo             
127#endif
Note: See TracBrowser for help on using the repository browser.