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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp @ 105

Last change on this file since 105 was 105, checked in by rosiere, 15 years ago
1) Bug fix : Load Miss Speculation (in Commit_unit, Update Prediction Table and Context State) 2) Change address, in rob write address_next. 3) Move Meta_Predictor in save directory
Property svn:keywords set to `Id`
File size: 28.0 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Context_State_transition.cpp 105 2009-02-05 11:18:31Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace context_state {
17
18
19	#undef FUNCTION
20	#define FUNCTION "Context_State::transition"
21	void Context_State::transition (void)
22	{
23	log_begin(Context_State,FUNCTION);
24	log_function(Context_State,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	for (uint32_t i=0; i<_param->_nb_context; i++)
29	{
30	reg_STATE [i] = CONTEXT_STATE_OK;
31	reg_INTERRUPT_ENABLE [i] = 0;
32	}
33	}
34	else
35	{
36	// -------------------------------------------------------------------
37	// -----[ next state ]------------------------------------------------
38	// -------------------------------------------------------------------
39	for (uint32_t i=0; i<_param->_nb_context; i++)
40	{
41	// uint32_t x = _param->_link_context_to_decod_unit [i];
42
43	Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
44	// Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
45
46	context_state_t state = reg_STATE [i];
47
48	switch (state)
49	{
50	case CONTEXT_STATE_OK :
51	{
52	// nothing, wait an event
53	break;
54	}
55	case CONTEXT_STATE_KO_EXCEP :
56	{
57	// Wait end of all instruction
58	if (inst_all == 0)
59	state = CONTEXT_STATE_KO_EXCEP_ADDR;
60	break;
61	}
62	case CONTEXT_STATE_KO_EXCEP_ADDR :
63	{
64	// nothing, wait the update of internal register (pc)
65	break;
66	}
67	case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND :
68	{
69	// Wait end of all instruction
70	if (inst_all == 0)
71
72	// state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
73	state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
74	break;
75	}
76	case CONTEXT_STATE_KO_MISS_LOAD_WAITEND :
77	{
78	// Wait end of all instruction
79	if (inst_all == 0)
80	state = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
81
82	break;
83	}
84	case CONTEXT_STATE_KO_EXCEP_SPR :
85	{
86	// nothing, wait the update of internal register (epcr, eear, sr, esr)
87	break;
88	}
89	case CONTEXT_STATE_KO_MISS_BRANCH_ADDR :
90	{
91	// nothing, wait the update of internal register (pc)
92	break;
93	}
94	case CONTEXT_STATE_KO_MISS_LOAD_ADDR :
95	{
96	// nothing, wait the update of internal register (pc)
97	break;
98	}
99	// case CONTEXT_STATE_KO_PSYNC :
100	// {
101	// // Wait end of all instruction
102	// if (inst_all == 0)
103	// state = CONTEXT_STATE_KO_PSYNC_FLUSH;
104	// break;
105	// }
106	case CONTEXT_STATE_KO_PSYNC_FLUSH :
107	{
108	// nothing, wait end of flush (ifetch)
109	if (inst_all == 0)
110	// state = CONTEXT_STATE_KO_PSYNC_ADDR;
111	state = CONTEXT_STATE_OK;
112
113	break;
114	}
115	case CONTEXT_STATE_KO_PSYNC_ADDR :
116	{
117	// nothing, wait the pc write
118	break;
119	}
120	// case CONTEXT_STATE_KO_CSYNC :
121	// {
122	// // Wait end of all instruction
123	// if (inst_all == 0)
124	// state = CONTEXT_STATE_KO_CSYNC_FLUSH;
125	// break;
126	// }
127	case CONTEXT_STATE_KO_CSYNC_FLUSH :
128	{
129	// nothing, wait end of flush (all internal structure)
130	if (inst_all == 0)
131	state = CONTEXT_STATE_KO_CSYNC_ADDR;
132	break;
133	}
134	case CONTEXT_STATE_KO_CSYNC_ADDR :
135	{
136	// nothing, wait the pc write
137	break;
138	}
139	// case CONTEXT_STATE_KO_MSYNC :
140	// {
141	// // Wait end of memory instruction
142	// if (inst_mem == 0)
143	// state = CONTEXT_STATE_KO_MSYNC_ISSUE;
144	// break;
145	// }
146	// case CONTEXT_STATE_KO_MSYNC_ISSUE :
147	// {
148	// // Wait the msync issue
149	// if (inst_mem != 0)
150	// state = CONTEXT_STATE_KO_MSYNC_EXEC;
151	// break;
152	// }
153	case CONTEXT_STATE_KO_MSYNC_EXEC :
154	{
155	// Wait the end of msync
156	if (inst_all == 0)
157	state = CONTEXT_STATE_OK;
158	break;
159	}
160	// case CONTEXT_STATE_KO_SPR :
161	// {
162	// // Wait end of all instruction
163	// if (inst_all == 0)
164	// state = CONTEXT_STATE_KO_SPR_ISSUE;
165	// break;
166	// }
167	// case CONTEXT_STATE_KO_SPR_ISSUE :
168	// {
169	// // Wait the spr_access issue
170	// if (inst_all != 0)
171	// state = CONTEXT_STATE_KO_SPR_EXEC;
172	// break;
173	// }
174	case CONTEXT_STATE_KO_SPR_EXEC :
175	{
176	// Wait the spr_access execution
177	if (inst_all == 0)
178	state = CONTEXT_STATE_OK;
179	break;
180	}
181
182	default :
183	{
184	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str()));
185	}
186	}
187	reg_STATE [i] = state;
188	}
189
190	// -------------------------------------------------------------------
191	// -----[ BRANCH_EVENT ]----------------------------------------------
192	// -------------------------------------------------------------------
193	for (uint32_t i=0; i<_param->_nb_context; ++i)
194	if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i])
195	{
196	log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i);
197
198	// throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n"));
199
200	context_state_t state = reg_STATE [i];
201
202	Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0;
203	Tdepth_t depth_cur = reg_EVENT_DEPTH [i];
204	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0;
205	Tdepth_t depth_max = _param->_array_size_depth [i];
206
207	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
208	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
209	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
210	Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
211
212	// priority : miss > excep > spr/sync
213	uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
214	uint8_t priority1 = 2; // miss
215
216	// is_valid = can modify local information
217	// if context_state_ok : yes
218	// if context_state_ko : test the depth, and the priority of event
219
220	bool is_valid = ((state == CONTEXT_STATE_OK) or
221	(depth1< depth0) or
222	((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth
223
224	if (is_valid)
225	{
226	Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
227	// reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
228	reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; //@@@ TODO : make MISS fast (miss decod)
229	reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot
230	reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next
231	reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val;
232	//reg_EVENT_ADDRESS_EEAR [i] = 0;
233	reg_EVENT_ADDRESS_EEAR_VAL [i] = 0;
234	reg_EVENT_IS_DELAY_SLOT [i] = 1;
235	reg_EVENT_IS_DS_TAKE [i] = dest_val;
236	reg_EVENT_DEPTH [i] = depth;
237	}
238	}
239
240	// -------------------------------------------------------------------
241	// -----[ DECOD_EVENT ]-----------------------------------------------
242	// -------------------------------------------------------------------
243
244	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
245	if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i])
246	{
247	log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i);
248
249	Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0;
250	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0;
251	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
252	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
253	Tdepth_t depth_max = _param->_array_size_depth [context];
254
255	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
256	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
257	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
258	Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
259
260	context_state_t state = reg_STATE [context];
261	Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]);
262
263	// miss > excep > spr/sync
264	uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
265	uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0;
266
267	// is_valid = can modify local information
268	// if context_state_ok : yes
269	// if context_state_ko : test the depth, and the priority of envent
270
271	bool is_valid = ((state == CONTEXT_STATE_OK) or
272	(depth1< depth0) or
273	((depth1==depth0) and (priority1>=priority0)));
274
275	if (is_valid)
276	{
277	log_printf(TRACE,Context_State,FUNCTION," * is_valid");
278
279	// decod :
280	// type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys)
281	context_state_t state_next = state;
282	Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]);
283	Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]);
284
285	switch (type)
286	{
287	case EVENT_TYPE_EXCEPTION :
288	{
289	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION");
290
291	state_next = CONTEXT_STATE_KO_EXCEP;
292
293	break;
294	}
295	case EVENT_TYPE_SPR_ACCESS :
296	{
297	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS");
298
299	// state_next = CONTEXT_STATE_KO_SPR ;
300	state_next = CONTEXT_STATE_KO_SPR_EXEC;
301	address++; // take next address
302	// if (is_delay_slot)
303	// throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
304	break;
305	}
306	case EVENT_TYPE_MSYNC :
307	{
308	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC");
309
310	// state_next = CONTEXT_STATE_KO_MSYNC;
311	state_next = CONTEXT_STATE_KO_MSYNC_EXEC;
312	address++; // take next address
313	// if (is_delay_slot)
314	// throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n");
315	break;
316	}
317	case EVENT_TYPE_PSYNC :
318	{
319	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC");
320
321	// state_next = CONTEXT_STATE_KO_PSYNC;
322	state_next = CONTEXT_STATE_KO_PSYNC_FLUSH;
323	address++; // take next address
324	if (is_delay_slot)
325	throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n");
326	break;
327	}
328	case EVENT_TYPE_CSYNC :
329	{
330	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC");
331
332	// state_next = CONTEXT_STATE_KO_CSYNC;
333	state_next = CONTEXT_STATE_KO_CSYNC_FLUSH;
334	address++; // take next address
335	if (is_delay_slot)
336	throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n");
337	break;
338	}
339	case EVENT_TYPE_NONE :
340	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
341	case EVENT_TYPE_LOAD_MISS_SPECULATION :
342	// case EVENT_TYPE_BRANCH_NO_ACCURATE :
343	default :
344	{
345	throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str()));
346	}
347	}
348
349	reg_STATE [context] = state_next;
350	reg_EVENT_ADDRESS [context] = address;
351	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]);
352	reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
353	//reg_EVENT_ADDRESS_EEAR [context]
354	reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;
355	reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot;
356	//reg_EVENT_IS_DS_TAKE [context] = 0;
357	reg_EVENT_DEPTH [context] = depth;
358	}
359	}
360
361	// -------------------------------------------------------------------
362	// -----[ COMMIT_EVENT ]----------------------------------------------
363	// -------------------------------------------------------------------
364
365	if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK )
366	{
367	log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT");
368
369	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0;
370	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0;
371	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
372	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
373	Tdepth_t depth_max = _param->_array_size_depth [context];
374
375	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
376	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
377	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
378	Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
379
380	context_state_t state = reg_STATE [context];
381	Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE );
382
383	// miss > excep > spr/sync
384	uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
385	uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION)
386
387	// is_valid = can modify local information
388	// if context_state_ok : yes
389	// if context_state_ko : test the depth, and the priority of envent
390
391	bool is_valid = ((state == CONTEXT_STATE_OK) or
392	(depth1< depth0) or
393	((depth1==depth0) and (priority1>=priority0)));
394
395	if (is_valid)
396	{
397	// commit
398	// type : exception
399	context_state_t state_next = state;
400	switch (type)
401	{
402	case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;}
403	case EVENT_TYPE_LOAD_MISS_SPECULATION : {state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; break;}
404	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
405	case EVENT_TYPE_SPR_ACCESS :
406	case EVENT_TYPE_MSYNC :
407	case EVENT_TYPE_PSYNC :
408	case EVENT_TYPE_CSYNC :
409	case EVENT_TYPE_NONE :
410	// case EVENT_TYPE_BRANCH_NO_ACCURATE :
411	default :
412	{
413	throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str()));
414	}
415	}
416	reg_STATE [context] = state_next;
417	reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS );
418	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR );
419	reg_EVENT_ADDRESS_EPCR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR_VAL );
420	reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR );
421	reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
422	reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT );
423	reg_EVENT_IS_DS_TAKE [context] = 0;
424	reg_EVENT_DEPTH [context] = depth;
425	}
426	}
427
428	// -------------------------------------------------------------------
429	// -----[ BRANCH_COMPLETE ]-------------------------------------------
430	// -------------------------------------------------------------------
431
432	// for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
433	// if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i])
434	// {
435	// log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i);
436	// if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))
437	// {
438	// Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
439	// Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
440	// Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
441	// Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
442	// Tdepth_t depth_max = _param->_array_size_depth [context];
443
444	// // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
445	// // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
446	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
447	// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
448
449	// context_state_t state = reg_STATE [context];
450
451	// // miss > excep > spr/sync
452	// uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
453	// uint8_t priority1 = 2; // miss
454
455	// // is_valid = can modify local information
456	// // if context_state_ok : yes
457	// // if context_state_ko : test the depth, and the priority of envent
458
459	// bool is_valid = ((state == CONTEXT_STATE_OK) or
460	// (depth1< depth0) or
461	// ((depth1==depth0) and (priority1>=priority0)));
462
463	// if (is_valid)
464	// {
465	// // commit
466	// Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]);
467	// reg_STATE [context] = CONTEXT_STATE_KO_MISS;
468	// reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT
469	// reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]);
470	// reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence
471	// //reg_EVENT_ADDRESS_EEAR [context];
472	// reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;
473	// reg_EVENT_IS_DELAY_SLOT [context] = take;
474	// reg_EVENT_IS_DS_TAKE [context] = take;
475	// reg_EVENT_DEPTH [context] = depth;
476	// }
477	// }
478	// }
479
480	// -------------------------------------------------------------------
481	// -----[ EVENT ]-----------------------------------------------------
482	// -------------------------------------------------------------------
483	for (uint32_t i=0; i<_param->_nb_context; i++)
484	if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i]))
485	{
486	log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i);
487	// Write pc
488	context_state_t state = reg_STATE [i];
489
490	switch (state)
491	{
492	case CONTEXT_STATE_KO_EXCEP_ADDR :
493	{
494	reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR;
495	break;
496	}
497	case CONTEXT_STATE_KO_MISS_BRANCH_ADDR:
498	// {
499	// reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
500	// break;
501	// }
502	case CONTEXT_STATE_KO_MISS_LOAD_ADDR :
503	case CONTEXT_STATE_KO_PSYNC_ADDR :
504	case CONTEXT_STATE_KO_CSYNC_ADDR :
505	{
506	reg_STATE [i] = CONTEXT_STATE_OK;
507	break;
508	}
509	default :
510	{
511	#ifdef DEBUG_TEST
512	throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
513	#endif
514	break;
515	}
516	}
517	}
518
519	// -------------------------------------------------------------------
520	// -----[ SPR_EVENT ]-------------------------------------------------
521	// -------------------------------------------------------------------
522	for (uint32_t i=0; i<_param->_nb_context; i++)
523	if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i]))
524	{
525	log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i);
526
527	// Write spr
528	#ifdef DEBUG_TEST
529	context_state_t state = reg_STATE [i];
530
531	if (state != CONTEXT_STATE_KO_EXCEP_SPR)
532	throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
533	#endif
534
535	reg_STATE [i] = CONTEXT_STATE_OK;
536	}
537
538	for (uint32_t i=0; i<_param->_nb_context; ++i)
539	{
540	reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]);
541
542	if (reg_INTERRUPT_ENABLE [i])
543	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i));
544	}
545	}
546
547	#if DEBUG >= DEBUG_TRACE
548	for (uint32_t i=0; i<_param->_nb_context; i++)
549	{
550	log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i);
551	log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str());
552	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2);
553	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2);
554	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]);
555	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2);
556	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]);
557	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]);
558	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]);
559	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
560	}
561	#endif
562
563	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
564	end_cycle ();
565	#endif
566
567	log_end(Context_State,FUNCTION);
568	};
569
570	}; // end namespace context_state
571	}; // end namespace front_end
572	}; // end namespace multi_front_end
573	}; // end namespace core
574
575	}; // end namespace behavioural
576	}; // end namespace morpheo
577	#endif

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