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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp @ 101

Last change on this file since 101 was 101, checked in by rosiere, 15 years ago
1) Add soc test 2) fix bug (Pc management, Decod and execute, Update prediction ...)
Property svn:keywords set to `Id`
File size: 26.7 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Context_State_transition.cpp 101 2009-01-15 17:19:08Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace context_state {
17
18
19	#undef FUNCTION
20	#define FUNCTION "Context_State::transition"
21	void Context_State::transition (void)
22	{
23	log_begin(Context_State,FUNCTION);
24	log_function(Context_State,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	for (uint32_t i=0; i<_param->_nb_context; i++)
29	{
30	reg_STATE [i] = CONTEXT_STATE_OK;
31	reg_INTERRUPT_ENABLE [i] = 0;
32	}
33	}
34	else
35	{
36	// -------------------------------------------------------------------
37	// -----[ next state ]------------------------------------------------
38	// -------------------------------------------------------------------
39	for (uint32_t i=0; i<_param->_nb_context; i++)
40	{
41	// uint32_t x = _param->_link_context_to_decod_unit [i];
42
43	Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
44	// Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
45
46	context_state_t state = reg_STATE [i];
47
48	switch (state)
49	{
50	case CONTEXT_STATE_OK :
51	{
52	// nothing, wait an event
53	break;
54	}
55	case CONTEXT_STATE_KO_EXCEP :
56	{
57	// Wait end of all instruction
58	if (inst_all == 0)
59	state = CONTEXT_STATE_KO_EXCEP_ADDR;
60	break;
61	}
62	case CONTEXT_STATE_KO_EXCEP_ADDR :
63	{
64	// nothing, wait the update of internal register (pc)
65	break;
66	}
67	case CONTEXT_STATE_KO_MISS_WAITEND :
68	{
69	// Wait end of all instruction
70	if (inst_all == 0)
71
72	// state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
73	state = CONTEXT_STATE_KO_MISS_ADDR;
74	break;
75	}
76	case CONTEXT_STATE_KO_EXCEP_SPR :
77	{
78	// nothing, wait the update of internal register (epcr, eear, sr, esr)
79	break;
80	}
81	case CONTEXT_STATE_KO_MISS_ADDR :
82	{
83	// nothing, wait the update of internal register (pc)
84	break;
85	}
86	// case CONTEXT_STATE_KO_PSYNC :
87	// {
88	// // Wait end of all instruction
89	// if (inst_all == 0)
90	// state = CONTEXT_STATE_KO_PSYNC_FLUSH;
91	// break;
92	// }
93	case CONTEXT_STATE_KO_PSYNC_FLUSH :
94	{
95	// nothing, wait end of flush (ifetch)
96	if (inst_all == 0)
97	// state = CONTEXT_STATE_KO_PSYNC_ADDR;
98	state = CONTEXT_STATE_OK;
99
100	break;
101	}
102	case CONTEXT_STATE_KO_PSYNC_ADDR :
103	{
104	// nothing, wait the pc write
105	break;
106	}
107	// case CONTEXT_STATE_KO_CSYNC :
108	// {
109	// // Wait end of all instruction
110	// if (inst_all == 0)
111	// state = CONTEXT_STATE_KO_CSYNC_FLUSH;
112	// break;
113	// }
114	case CONTEXT_STATE_KO_CSYNC_FLUSH :
115	{
116	// nothing, wait end of flush (all internal structure)
117	if (inst_all == 0)
118	state = CONTEXT_STATE_KO_CSYNC_ADDR;
119	break;
120	}
121	case CONTEXT_STATE_KO_CSYNC_ADDR :
122	{
123	// nothing, wait the pc write
124	break;
125	}
126	// case CONTEXT_STATE_KO_MSYNC :
127	// {
128	// // Wait end of memory instruction
129	// if (inst_mem == 0)
130	// state = CONTEXT_STATE_KO_MSYNC_ISSUE;
131	// break;
132	// }
133	// case CONTEXT_STATE_KO_MSYNC_ISSUE :
134	// {
135	// // Wait the msync issue
136	// if (inst_mem != 0)
137	// state = CONTEXT_STATE_KO_MSYNC_EXEC;
138	// break;
139	// }
140	case CONTEXT_STATE_KO_MSYNC_EXEC :
141	{
142	// Wait the end of msync
143	if (inst_all == 0)
144	state = CONTEXT_STATE_OK;
145	break;
146	}
147	// case CONTEXT_STATE_KO_SPR :
148	// {
149	// // Wait end of all instruction
150	// if (inst_all == 0)
151	// state = CONTEXT_STATE_KO_SPR_ISSUE;
152	// break;
153	// }
154	// case CONTEXT_STATE_KO_SPR_ISSUE :
155	// {
156	// // Wait the spr_access issue
157	// if (inst_all != 0)
158	// state = CONTEXT_STATE_KO_SPR_EXEC;
159	// break;
160	// }
161	case CONTEXT_STATE_KO_SPR_EXEC :
162	{
163	// Wait the spr_access execution
164	if (inst_all == 0)
165	state = CONTEXT_STATE_OK;
166	break;
167	}
168
169	default :
170	{
171	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str()));
172	}
173	}
174	reg_STATE [i] = state;
175	}
176
177	// -------------------------------------------------------------------
178	// -----[ BRANCH_EVENT ]----------------------------------------------
179	// -------------------------------------------------------------------
180	for (uint32_t i=0; i<_param->_nb_context; ++i)
181	if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i])
182	{
183	log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i);
184
185	// throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n"));
186
187	context_state_t state = reg_STATE [i];
188
189	Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0;
190	Tdepth_t depth_cur = reg_EVENT_DEPTH [i];
191	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0;
192	Tdepth_t depth_max = _param->_array_size_depth [i];
193
194	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
195	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
196	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
197	Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
198
199	// priority : miss > excep > spr/sync
200	uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
201	uint8_t priority1 = 2; // miss
202
203	// is_valid = can modify local information
204	// if context_state_ok : yes
205	// if context_state_ko : test the depth, and the priority of event
206
207	bool is_valid = ((state == CONTEXT_STATE_OK) or
208	(depth1< depth0) or
209	((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth
210
211	if (is_valid)
212	{
213	Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
214	// reg_STATE [i] = CONTEXT_STATE_KO_MISS_ADDR;
215	reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
216	reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot
217	reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next
218	reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val;
219	//reg_EVENT_ADDRESS_EEAR [i] = 0;
220	reg_EVENT_ADDRESS_EEAR_VAL [i] = 0;
221	reg_EVENT_IS_DELAY_SLOT [i] = 1;
222	reg_EVENT_IS_DS_TAKE [i] = dest_val;
223	reg_EVENT_DEPTH [i] = depth;
224	}
225	}
226
227	// -------------------------------------------------------------------
228	// -----[ DECOD_EVENT ]-----------------------------------------------
229	// -------------------------------------------------------------------
230
231	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
232	if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i])
233	{
234	log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i);
235
236	Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0;
237	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0;
238	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
239	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
240	Tdepth_t depth_max = _param->_array_size_depth [context];
241
242	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
243	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
244	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
245	Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
246
247	context_state_t state = reg_STATE [context];
248	Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]);
249
250	// miss > excep > spr/sync
251	uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
252	uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0;
253
254	// is_valid = can modify local information
255	// if context_state_ok : yes
256	// if context_state_ko : test the depth, and the priority of envent
257
258	bool is_valid = ((state == CONTEXT_STATE_OK) or
259	(depth1< depth0) or
260	((depth1==depth0) and (priority1>priority0)));
261
262	if (is_valid)
263	{
264	log_printf(TRACE,Context_State,FUNCTION," * is_valid");
265
266	// decod :
267	// type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys)
268	context_state_t state_next = state;
269	Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]);
270	Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]);
271
272	switch (type)
273	{
274	case EVENT_TYPE_EXCEPTION :
275	{
276	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION");
277
278	state_next = CONTEXT_STATE_KO_EXCEP;
279
280	break;
281	}
282	case EVENT_TYPE_SPR_ACCESS :
283	{
284	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS");
285
286	// state_next = CONTEXT_STATE_KO_SPR ;
287	state_next = CONTEXT_STATE_KO_SPR_EXEC;
288	address++; // take next address
289	// if (is_delay_slot)
290	// throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
291	break;
292	}
293	case EVENT_TYPE_MSYNC :
294	{
295	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC");
296
297	// state_next = CONTEXT_STATE_KO_MSYNC;
298	state_next = CONTEXT_STATE_KO_MSYNC_EXEC;
299	address++; // take next address
300	// if (is_delay_slot)
301	// throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n");
302	break;
303	}
304	case EVENT_TYPE_PSYNC :
305	{
306	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC");
307
308	// state_next = CONTEXT_STATE_KO_PSYNC;
309	state_next = CONTEXT_STATE_KO_PSYNC_FLUSH;
310	address++; // take next address
311	if (is_delay_slot)
312	throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n");
313	break;
314	}
315	case EVENT_TYPE_CSYNC :
316	{
317	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC");
318
319	// state_next = CONTEXT_STATE_KO_CSYNC;
320	state_next = CONTEXT_STATE_KO_CSYNC_FLUSH;
321	address++; // take next address
322	if (is_delay_slot)
323	throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n");
324	break;
325	}
326	case EVENT_TYPE_NONE :
327	case EVENT_TYPE_MISS_SPECULATION :
328	case EVENT_TYPE_BRANCH_NO_ACCURATE :
329	default :
330	{
331	throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str()));
332	}
333	}
334
335	reg_STATE [context] = state_next;
336	reg_EVENT_ADDRESS [context] = address;
337	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]);
338	reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
339	//reg_EVENT_ADDRESS_EEAR [context]
340	reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;
341	reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot;
342	//reg_EVENT_IS_DS_TAKE [context] = 0;
343	reg_EVENT_DEPTH [context] = depth;
344	}
345	}
346
347	// -------------------------------------------------------------------
348	// -----[ COMMIT_EVENT ]----------------------------------------------
349	// -------------------------------------------------------------------
350
351	if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK )
352	{
353	log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT");
354
355	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0;
356	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0;
357	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
358	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
359	Tdepth_t depth_max = _param->_array_size_depth [context];
360
361	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
362	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
363	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
364	Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
365
366	context_state_t state = reg_STATE [context];
367	Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE );
368
369	// miss > excep > spr/sync
370	uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
371	uint8_t priority1 = 1; // exception
372
373	// is_valid = can modify local information
374	// if context_state_ok : yes
375	// if context_state_ko : test the depth, and the priority of envent
376
377	bool is_valid = ((state == CONTEXT_STATE_OK) or
378	(depth1< depth0) or
379	((depth1==depth0) and (priority1>priority0)));
380
381	if (is_valid)
382	{
383	// commit
384	// type : exception
385	context_state_t state_next = state;
386	switch (type)
387	{
388	case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;}
389	case EVENT_TYPE_SPR_ACCESS :
390	case EVENT_TYPE_MSYNC :
391	case EVENT_TYPE_PSYNC :
392	case EVENT_TYPE_CSYNC :
393	case EVENT_TYPE_NONE :
394	case EVENT_TYPE_MISS_SPECULATION :
395	case EVENT_TYPE_BRANCH_NO_ACCURATE :
396	default :
397	{
398	throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str()));
399	}
400	}
401	reg_STATE [context] = state_next;
402	reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS );
403	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR );
404	reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
405	reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR );
406	reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
407	reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT );
408	//reg_EVENT_IS_DS_TAKE [context] = 0;
409	reg_EVENT_DEPTH [context] = depth;
410	}
411	}
412
413	// -------------------------------------------------------------------
414	// -----[ BRANCH_COMPLETE ]-------------------------------------------
415	// -------------------------------------------------------------------
416
417	// for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
418	// if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i])
419	// {
420	// log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i);
421	// if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))
422	// {
423	// Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
424	// Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
425	// Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
426	// Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
427	// Tdepth_t depth_max = _param->_array_size_depth [context];
428
429	// // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
430	// // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
431	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
432	// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
433
434	// context_state_t state = reg_STATE [context];
435
436	// // miss > excep > spr/sync
437	// uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
438	// uint8_t priority1 = 2; // miss
439
440	// // is_valid = can modify local information
441	// // if context_state_ok : yes
442	// // if context_state_ko : test the depth, and the priority of envent
443
444	// bool is_valid = ((state == CONTEXT_STATE_OK) or
445	// (depth1< depth0) or
446	// ((depth1==depth0) and (priority1>priority0)));
447
448	// if (is_valid)
449	// {
450	// // commit
451	// Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]);
452	// reg_STATE [context] = CONTEXT_STATE_KO_MISS;
453	// reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT
454	// reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]);
455	// reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence
456	// //reg_EVENT_ADDRESS_EEAR [context];
457	// reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;
458	// reg_EVENT_IS_DELAY_SLOT [context] = take;
459	// reg_EVENT_IS_DS_TAKE [context] = take;
460	// reg_EVENT_DEPTH [context] = depth;
461	// }
462	// }
463	// }
464
465	// -------------------------------------------------------------------
466	// -----[ EVENT ]-----------------------------------------------------
467	// -------------------------------------------------------------------
468	for (uint32_t i=0; i<_param->_nb_context; i++)
469	if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i]))
470	{
471	log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i);
472	// Write pc
473	context_state_t state = reg_STATE [i];
474
475	switch (state)
476	{
477	case CONTEXT_STATE_KO_EXCEP_ADDR :
478	{
479	reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR;
480	break;
481	}
482	case CONTEXT_STATE_KO_MISS_ADDR :
483	// {
484	// reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
485	// break;
486	// }
487	case CONTEXT_STATE_KO_PSYNC_ADDR :
488	case CONTEXT_STATE_KO_CSYNC_ADDR :
489	{
490	reg_STATE [i] = CONTEXT_STATE_OK;
491	break;
492	}
493	default :
494	{
495	#ifdef DEBUG_TEST
496	throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
497	#endif
498	break;
499	}
500	}
501	}
502
503	// -------------------------------------------------------------------
504	// -----[ SPR_EVENT ]-------------------------------------------------
505	// -------------------------------------------------------------------
506	for (uint32_t i=0; i<_param->_nb_context; i++)
507	if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i]))
508	{
509	log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i);
510
511	// Write spr
512	#ifdef DEBUG_TEST
513	context_state_t state = reg_STATE [i];
514
515	if (state != CONTEXT_STATE_KO_EXCEP_SPR)
516	throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
517	#endif
518
519	reg_STATE [i] = CONTEXT_STATE_OK;
520	}
521
522	for (uint32_t i=0; i<_param->_nb_context; ++i)
523	{
524	reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]);
525
526	if (reg_INTERRUPT_ENABLE [i])
527	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i));
528	}
529	}
530
531	#if DEBUG >= DEBUG_TRACE
532	for (uint32_t i=0; i<_param->_nb_context; i++)
533	{
534	log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i);
535	log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str());
536	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2);
537	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2);
538	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]);
539	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2);
540	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]);
541	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]);
542	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]);
543	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
544	}
545	#endif
546
547	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
548	end_cycle ();
549	#endif
550
551	log_end(Context_State,FUNCTION);
552	};
553
554	}; // end namespace context_state
555	}; // end namespace front_end
556	}; // end namespace multi_front_end
557	}; // end namespace core
558
559	}; // end namespace behavioural
560	}; // end namespace morpheo
561	#endif

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